vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells

In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorizationPreprin

Hardware Considerations for Signal Processing Systems: A Step Toward the Unconventional.

As we progress into the future, signal processing algorithms are becoming more computationally intensive and power hungry while the desire for mobile products and low power devices is also increasing. An integrated ASIC solution is one of the primary ways chip developers can improve performance and add functionality while keeping the power budget low. This work discusses ASIC hardware for both conventional and unconventional signal processing systems, and how integration, error resilience, emerging devices, and new algorithms can be leveraged by signal processing systems to further improve performance and enable new applications. Specifically this work presents three case studies: 1) a conventional and highly parallel mix signal cross-correlator ASIC for a weather satellite performing real-time synthetic aperture imaging, 2) an unconventional native stochastic computing architecture enabled by memristors, and 3) two unconventional sparse neural network ASICs for feature extraction and object classification. As improvements from technology scaling alone slow down, and the demand for energy efficient mobile electronics increases, such optimization techniques at the device, circuit, and system level will become more critical to advance signal processing capabilities in the future.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116685/1/knagphil_1.pd

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine

Robust laser-free entanglement with trapped ions

Trapped ions with microwave radiation are a promising platform for universal quantum computing. However, a major obstacle in the way of scalability is the coupling of the qubits to their noisy environment. This thesis offers means to improve the fidelity of two-qubit entangling gates. To this end, we investigate noise from classical control hardware and study quantum control methods that increase the gate’s robustness. The noise spectrums of classical control hardware typically exhibit non-Markovian behaviour. Therefore, a transfer function in frequency space is derived for each source, transforming hardware noise to qubit-frame noise. It is found that voltage noise on the electrodes is a significant contribution to decoherence as it displaces the ions within the static magnetic field gradient. We propose and demonstrate a voltage noise cancellation scheme that is compatible with microfabricated surface traps. We then identify a library of quantum control methods that increase the robustness of a bichromatic interaction to both spin and motional decoherence. We also propose a novel σz ⊗ σz entangling gate which makes use of the intrinsic J-coupling interaction of ions in a static magnetic gradient. The resulting interaction is virtually insensitive to motional decoherence, which alleviates stringent experimental requirements. We finally demonstrate a bichromatic interaction that is simultaneously robust to spin and motional decoherence, by means of continuous dynamical decoupling and phase modulation on the sidebands. Recalling that noise in the ion’s position couples into magnetic field noise due to the static magnetic field gradient, we use this noise mechanism as the basis of a promising electric field sensor. We experimentally demonstrate AC electrometry with a sensitivity of S = 7.0(5)mVm−1Hz−1/2. Noise spectroscopy was also demonstrated and was limited by the noise floor, where the minimum sensitivity was 545 nVm−1Hz−1/2.Open Acces

SIRU development. Volume 1: System development

A complete description of the development and initial evaluation of the Strapdown Inertial Reference Unit (SIRU) system is reported. System development documents the system mechanization with the analytic formulation for fault detection and isolation processing structure; the hardware redundancy design and the individual modularity features; the computational structure and facilities; and the initial subsystem evaluation results

Improving fault tolerant drives for aerospace applications

D EngThe aerospace industry is moving towards the more electric aeroplane where traditional hydraulic systems are being replaced with electrical systems. Electrical technology offers some strong advantages compared to hydraulic technology including; cost, efficiency, power on demand and relative ease of maintenance. As with most new technologies, a major disadvantage is its limited reliability history. A lot of research in the aerospace field therefore focuses on improving fault tolerant electrical systems. Work done in this thesis builds on an existing fault tolerant drive, developed by Newcastle University and Goodrich Actuation Systems as part of the ELGEAR (Electrical Landing Gear) project. The purpose of this work is to continue improving the drive’s fault tolerant features; especially in areas where the drive is most vulnerable. The first part of this thesis focuses on improving the overall system reliability by monitoring the health of the dc-link capacitors in the fault tolerant drive. The implemented estimation technique makes use of voltage and current sensors which are already in place for protection and control purposes. The novel aspect of the proposed technique relates to monitoring capacitors in real time whilst the motor is operational. No external interferences, such as injected signals or special operation of the drive, are required. The condition monitoring system is independent of torque and speed, and hence independent of a variation in load. The work was validated using analytical methods, simulation, low voltage experimentation and high voltage implementation on the ELGEAR drive. The second part of this thesis focuses on single shorted turn faults, in fault tolerant permanent magnet (PM) motors. Despite the motor being able to withstand a wide range of faults, the single shorted turn fault remains a difficult fault to detect and handle. The problem arises from the magnets on the spinning rotor that cannot be ‘turned off’ at will. This thesis investigates the severity of the faulted current in a shorted turn and how it varies depending on the turn’s location in the stator slot. The severity of the fault is studied using 2D finite element analysis and practical implementation on the ELGEAR rig. Finally, recommendations are proposed for improving the ELGEAR motor for future fault tolerant designs.EPRSC and Goodrich Aerospace (now United Technologies

STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS

Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy particle from such an environment may cause voltage/current transients, thereby inducing Single Event Effect (SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975, this community has made tremendous progress in investigating the mechanisms of SEE and exploring radiation tolerant techniques. However, as the IC technology advances, the existing hardening techniques have been rendered less effective because of the reduced spacing and charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has identified radiation-induced soft errors as the major threat to the reliable operation of electronic systems in the future. In digital systems, hardening techniques of their core components, such as latches, logic, and clock network, need to be addressed. Two single event tolerant latch designs taking advantage of feedback transistors are presented and evaluated in both single event resilience and overhead. These feedback transistors are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in a larger feedback delay and higher single event tolerance. On the other hand, these extra transistors are turned ON when the cell is in the write mode. As a result, no significant write delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section when compared to the reference cells. Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The worst case occurs when the output is evaluated logic high, where the pull-up networks are turned OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail. A capacitor added to the feedback path increases the node capacitance of the output and the feedback delay, thereby increasing the single event critical charge. Another differential structure that has two differential inputs and outputs eliminates single event upset issues at the expense of an increased number of transistors. Clock networks in advanced technology nodes may cause significant errors in an IC as the devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme in a digital system. It was fabricated in a 28nm technology and evaluated through the use of heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was demonstrated during these tests. In addition to mitigating single event issues by using hardened designs, built-in current sensors can be used to detect single event induced currents in the n-well and, if implemented, subsequently execute fault correction actions. These sensors were simulated and fabricated in a 28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of this sensor design. This manifests itself as an alternative to existing hardening techniques. In conclusion, this work investigates single event effects in digital systems, especially those in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock, and current sensor designs have been presented and evaluated. Through the use of these designs, the single event tolerance of a digital system can be achieved at the expense of varying overhead in terms of area, power, and delay

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy