High Temperature Electronics Design for Aero Engine Controls and Health Monitoring

There is a growing desire to install electronic power and control systems in high temperature harsh environments to improve the accuracy of critical measurements, reduce the amount of cabling and to eliminate cooling systems. Typical target applications include electronics for energy exploration, power generation and control systems. Technical topics presented in this book include:• High temperature electronics market• High temperature devices, materials and assembly processes• Design, manufacture and testing of multi-sensor data acquisition system for aero-engine control• Future applications for high temperature electronicsHigh Temperature Electronics Design for Aero Engine Controls and Health Monitoring contains details of state of the art design and manufacture of electronics targeted towards a high temperature aero-engine application. High Temperature Electronics Design for Aero Engine Controls and Health Monitoring is ideal for design, manufacturing and test personnel in the aerospace and other harsh environment industries as well as academic staff and master/research students in electronics engineering, materials science and aerospace engineering

High Temperature Electronics Design for Aero Engine Controls and Health Monitoring

There is a growing desire to install electronic power and control systems in high temperature harsh environments to improve the accuracy of critical measurements, reduce the amount of cabling and to eliminate cooling systems. Typical target applications include electronics for energy exploration, power generation and control systems. Technical topics presented in this book include:• High temperature electronics market• High temperature devices, materials and assembly processes• Design, manufacture and testing of multi-sensor data acquisition system for aero-engine control• Future applications for high temperature electronicsHigh Temperature Electronics Design for Aero Engine Controls and Health Monitoring contains details of state of the art design and manufacture of electronics targeted towards a high temperature aero-engine application. High Temperature Electronics Design for Aero Engine Controls and Health Monitoring is ideal for design, manufacturing and test personnel in the aerospace and other harsh environment industries as well as academic staff and master/research students in electronics engineering, materials science and aerospace engineering

Study report recommendations for the next generation Range Safety System (RSS) Integrated Receiver/Decoder (IRD)

The Integrated Receiver/Decoder (IRD) currently used on the Space Shuttle was designed in the 1980 and prior time frame. Over the past 12 years, several parts have become obsolete or difficult to obtain. As directed by the Marshall Space Flight Center, a primary objective is to investigate updating the IRD design using the latest technology subsystems. To take advantage of experience with the current designs, an analysis of failures and a review of discrepancy reports, material review board actions, scrap, etc. are given. A recommended new design designated as the Advanced Receiver/Decoder (ARD) is presented. This design uses the latest technology components to simplify circuits, improve performance, reduce size and cost, and improve reliability. A self-test command is recommended that can improve and simplify operational procedures. Here, the new design is contrasted with the old. Possible simplification of the total Range Safety System is discussed, as is a single-step crypto technique that can improve and simplify operational procedures

High Efficiency Polymer based Direct Multi-jet Impingement Cooling Solution for High Power Devices

Liquid jet impingement cooling is an efficient cooling technique where the liquid coolant is directly ejected from nozzles on the chip backside resulting in a high cooling efficiency due to the absence of the TIM and the lateral temperature gradient. In literature, several Si-fabrication based impingement coolers with nozzle diameters of a few distributed returns or combination of micro-channels and impingement nozzles. The drawback of this Si processing of the cooler is the high fabrication cost. Other fabrication methods for nozzle diameters for ceramic and metal. Low cost fabrication methods, including injection molding and 3D printing have been introduced for much larger nozzle diameters (mm range) with larger cooler dimensions. These dimensions and processes are however not compatible with the chip packaging process flow. This PhD focuses on the modeling, design, fabrication and characterization of a micro-scale liquid impingement cooler using advanced, yet cost efficient, fabrication techniques. The main objectives are: (a) development of a modeling methodology to optimize the cooler geometry; (b) exploring low cost fabrication methods for the package level impingement jet cooler; (c) experimental thermal and hydraulic characterization and analysis of the fabricated coolers; (d) applying the direct impingement jet cooling solutions to different applications

Digitally driven microfabrication of 3D multilayer embedded electronic systems

The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques. A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies. This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages. The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry. Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation. The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm. A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved. The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure. These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure. SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal. DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code. The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high. Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 3.68 (height of 2mm and diameter of 550μm). Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity. A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation. ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer. Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process. After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane. A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers. This complete procedure could be repeated numerous times to fabricate multilayer electronic devices. This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads. The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways. Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch. A flip-chip bonding force of 0.08 N resulted in a contact resistance of 2.3 Ω at a standoff height of ~80 μm. Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful. Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis. This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality

Study of intermetallic compound layer formation, growth and evaluation of shear strength of lead-free solder joints

Solder joints play a very important role in electronic products as the integrity of electronics packaging and assembly rests on the quality of these connections. The increasing demands for higher performance, lower cost, and miniaturisation in hand-held and consumer electronic products have led to the use of dense interconnections. This miniaturization trend means that solder joint reliability remains an important challenge with surface mount electronics assembly, especially those used in hostile environments, and applications such as automobile, aerospace and other safety critical operations. One of the most important factors which are known to affect solder joint reliability is the thickness of intermetallic compound (IMC) layer formed between the solder and the substrate. Although the formation of an IMC layer signifies good bonding between the solder and substrate, its main disadvantage is that it is also known to be the most brittle part of the solder joint. Thus as the miniaturisation trend continues, and solder joints become even smaller in size, the nature and impact of IMC layer thickness on solder joint reliability becomes even more of a concern with the introduction of new lead-free soldering. Other factors which are known to affect solder joint reliability include the bonding strength, the voiding percentage in joints, the size of the voids and their location within the joint. The work reported in this thesis on formation and growth of intermetallic compound layer, and evaluation of the shear strength of lead-free solder joints is divided into four main parts. The first part of the study is concerned with understanding of the effect of pad sizes on Inter-metallic compound layer formation and growth for lead-free solder joints. The second part concerns the study of the effect of temperature cycling and reflow profiles on intermetallic growth between Sn-Ag-Cu alloy and Cu substrate. The third part of the study concerns the investigation of the effect of reflow soldering profile optimization on solder volumes using design of experiment technique. The focus of the final part of the study is the investigation of the effect of Inter-metallic Compound thickness on shear strength of 1206 surface mount chip resistor. The results from the experimental work showed that the pad size has very little influence on the growth of the IMC. The result also shows that the growth of IMC depends on diffusion rate, temperature and time according to the power-law model; and that the IMC layer thickness is independent of pad size. The significance of this result is that with further reductions in joint size (with IMC layer thickness remaining the same), the ratio of the IMC layer thickness to solder joint size will increase and adversely impact the joint reliability. The work carried out on ageing temperatures and reflow profiles of Sn-Ag-Cu alloy and Cu substrate also showed the reaction-diffusion mechanism of intermetallic compound formation and growth in solder joints. The study also showed that the most significant factor in achieving lower IMC layer thickness and fine microstructures is the time to peak temperature of the reflow soldering process. The effect of IMC layer thickness on the shear strength of Sn-Ag-Cu solder joints was investigated. The relationship of shear strength, interfacial microstructures and fracture surfaces was considered. It is clear that formation of continuous Cu-Sn and SnNiCu layers are the reason for the weak interface strength. The results show that the shear strength of solder joints decreases with increasing ageing time. The results of this study have been disseminated through journal and conference publications and will be of interest to R&D personnel working in the area of high temperature electronics and in particular those working in the field of automotive electronics

Thermo-mechanical reliability studies of lead-free solder interconnects

N/ASolder interconnections, also known as solder joints, are the weakest link in electronics packaging. Reliability of these miniature joints is of utmost interest - especially in safety-critical applications in the automotive, medical, aerospace, power grid and oil and drilling sectors. Studies have shown that these joints' critical thermal and mechanical loading culminate in accelerated creep, fatigue, and a combination of these joints' induced failures. The ball grid array (BGA) components being an integral part of many electronic modules functioning in mission-critical systems. This study investigates the response of solder joints in BGA to crucial reliability influencing parameters derived from creep, visco-plastic and fatigue damage of the joints. These are the plastic strain, shear strain, plastic shear strain, creep energy density, strain energy density, deformation, equivalent (Von-Mises) stress etc. The parameters' obtained magnitudes are inputted into established life prediction models – Coffin-Manson, Engelmaier, Solomon (Low cycle fatigue) and Syed (Accumulated creep energy density) – to determine several BGA assemblies' fatigue lives. The joints are subjected to thermal, mechanical and random vibration loadings. The finite element analysis (FEA) is employed in a commercial software package to model and simulate the responses of the solder joints of the representative assemblies' finite element models. As the magnitude and rate of degradation of solder joints in the BGA significantly depend on the composition of the solder alloys used to assembly the BGA on the printed circuit board, this research studies the response of various mainstream lead-free Sn-Ag-Cu (SAC) solders (SAC305, SAC387, SAC396 and SAC405) and benchmarked those with lead-based eutectic solder (Sn63Pb37). In the creep response study, the effects of thermal ageing and temperature cycling on these solder alloys' behaviours are explored. The results show superior creep properties for SAC405 and SAC396 lead-free solder alloys. The lead-free SAC405 solder joint is the most effective solder under thermal cycling condition, and the SAC396 solder joint is the most effective solder under isothermal ageing operation. The finding shows that SAC405 and SAC396 solders accumulated the minimum magnitudes of stress, strain rate, deformation rate and strain energy density than any other solder considered in this study. The hysteresis loops show that lead-free SAC405 has the lowest dissipated energy per cycle. Thus the highest fatigue life, followed by eutectic lead-based Sn63Pb37 solder. The solder with the highest dissipated energy per cycle was lead-free SAC305, SAC387 and SAC396 solder alloys. In the thermal fatigue life prediction research, four different lead-free (SAC305, SAC387, SAC396 and SAC405) and one eutectic lead-based (Sn63Pb37) solder alloys are defined against their thermal fatigue lives (TFLs) to predict their mean-time-to-failure for preventive maintenance advice. Five finite elements (FE) models of the assemblies of the BGAs with the different solder alloy compositions and properties are created with SolidWorks. The models are subjected to standard IEC 60749-25 temperature cycling in ANSYS 19.0 mechanical package environment. SAC405 joints have the highest predicted TFL of circa 13.2 years, while SAC387 joints have the least life of circa 1.4 years. The predicted lives are inversely proportional to the magnitude of the areas of stress-strain hysteresis loops of the solder joints. The prediction models are significantly consistent in predicted magnitudes across the solder joints irrespective of the damage parameters used. Several failure modes drive solder joints and damage mechanics from the research and understand an essential variation in the models' predicted values. This investigation presents a method of managing preventive maintenance time of BGA electronic components in mission-critical systems. It recommends developing a novel life prediction model based on a combination of the damage parameters for enhanced prediction. The FEA random vibration simulation test results showed that different solder alloys have a comparable performance during random vibration testing. The fatigue life result shows that SAC405 and SAC396 have the highest fatigue lives before being prone to failure. As a result of the FEA simulation outcomes with the application of Coffin-Manson's empirical formula, the author can predict the fatigue life of solder joint alloys to a higher degree of accuracy of average ~93% in an actual service environment such as the one experienced under-the-hood of an automobile and aerospace. Therefore, it is concluded that the combination of FEA simulation and empirical formulas employed in this study could be used in the computation and prediction of the fatigue life of solder joint alloys when subjected to random vibration. Based on the thermal and mechanical responses of lead-free SAC405 and SAC396 solder alloys, they are recommended as a suitable replacement of lead-based eutectic Sn63Pb37 solder alloy for improved device thermo-mechanical operations when subjected to random vibration (non-deterministic vibration). The FEA simulation studies' outcomes are validated using experimental and analytical-based reviews in published and peer-reviewed literature.N/

An experimental assessment of computational fluid dynamics predictive accuracy for electronic component operational temperature

Ever-rising Integrated Circuit (IC) power dissipation, combined with reducing product development cycles times, have placed increasing reliance on the use of Computational Fluid Dynamics (CFD) software for the thermal analysis of electronic equipment. In this study, predictive accuracy is assessed for board-mounted electronic component heat transfer using both a CFD code dedicated to the thermal analysis of electronics, Flotherm, and a general-purpose CFD code, Fluent. Using Flotherm, turbulent flow modelling approaches typically employed for the analysis of electronics cooling, namely algebraic mixing length and two-equation high-Reynolds number k-e models, are assessed. As shown, such models are not specific for the analysis of forced airflows over populated electronic boards, which are typically classified as low-Reynolds number flows. The potential for improved predictive accuracy is evaluated using candidate turbulent flow models more suited to such flows, namely a one-equation SpalartAllmaras model, two-layer zonal model and two equation SST k-co model, all implemented in Fluent. Numerical predictions are compared with experimental benchmark data for a range of componentboard topologies generating different airflow phenomena and varying degrees of component thermal interaction. Test case complexity is incremented in controlled steps, from single board-mounted components in free convection, to forced air-cooled, multi-component board configurations. Apart from the prediction of component operational temperature, the application of CFD analysis to the design of electronic component reliability screens and convective solder reflow temperature profiles is also investigated. Benchmark criteria are based on component junction temperature and component-board surface temperature profiles, measured using thermal test chips and infrared thermography respectively. This data is supplemented by experimental visualisations of the forced airflows over the boards, which are used to help assess predictive accuracy. Component numerical modelling is based on nominal package dimensions and material thermal properties. To eliminate potential numerical modelling uncertainties, both the test component geometry and structural integrity are assessed using destructive and non-destructive testing. While detailed component modelling provides the à priori junction temperature predictions, the capability of compact thermal models to predict multi-mode component heat transfer is also assessed. In free convection, component junction temperature predictions for an in-line array of fifteen boardmounted components are within ±5°C or 7% of measurement. Predictive accuracy decays up to ±20°C or 35% in forced airflows using the k-e flow model. Furthermore, neither the laminar or k-e turbulent flow model accurately resolve the complete flow fields over the boards, suggesting the need for a turbulence model capable of modelling transition. Using a k-co model, significant improvements in junction temperature prediction accuracy are obtained, which are associated with improved prediction of both board leading edge heat transfer and component thermal interaction. Whereas with the k-e flow model, prediction accuracy would only be sufficient for the early to intermediate phase of a thermal design process, the use of the k-co model would enable parametric analysis of product thermal performance to be undertaken with greater confidence. Such models would also permit the generation of more accurate temperature boundary conditions for use in Physics-of-Failure (PoF) based component reliability prediction methods. The case is therefore made for vendors of CFD codes dedicated to the thermal analysis of electronics to consider the adoption of eddy viscosity turbulence models more suited to the analysis of component heat transfer. While this study ultimately highlights that electronic component operational temperature needs to be experimentally measured to quality product thermal performance and reliability, the use of such flow models would help reduce the current dependency on experimental prototyping. This would not only enhance the potential of CFD as a design tool, but also its capability to provide detailed insight into complex multi-mode heat transfer, that would otherwise be difficult to characterise experimentally

Advanced sensors technology survey

This project assesses the state-of-the-art in advanced or 'smart' sensors technology for NASA Life Sciences research applications with an emphasis on those sensors with potential applications on the space station freedom (SSF). The objectives are: (1) to conduct literature reviews on relevant advanced sensor technology; (2) to interview various scientists and engineers in industry, academia, and government who are knowledgeable on this topic; (3) to provide viewpoints and opinions regarding the potential applications of this technology on the SSF; and (4) to provide summary charts of relevant technologies and centers where these technologies are being developed