Tree-Residue Vertex-Breaking: a new tool for proving hardness

In this paper, we introduce a new problem called Tree-Residue Vertex-Breaking (TRVB): given a multigraph G some of whose vertices are marked "breakable," is it possible to convert G into a tree via a sequence of "vertex-breaking" operations (replacing a degree-k breakable vertex by k degree-1 vertices, disconnecting the k incident edges)? We characterize the computational complexity of TRVB with any combination of the following additional constraints: G must be planar, G must be a simple graph, the degree of every breakable vertex must belong to an allowed list B, and the degree of every unbreakable vertex must belong to an allowed list U. The two results which we expect to be most generally applicable are that (1) TRVB is polynomially solvable when breakable vertices are restricted to have degree at most 3; and (2) for any k >= 4, TRVB is NP-complete when the given multigraph is restricted to be planar and to consist entirely of degree-k breakable vertices. To demonstrate the use of TRVB, we give a simple proof of the known result that Hamiltonicity in max-degree-3 square grid graphs is NP-hard. We also demonstrate a connection between TRVB and the Hypergraph Spanning Tree problem. This connection allows us to show that the Hypergraph Spanning Tree problem in k-uniform 2-regular hypergraphs is NP-complete for any k >= 4, even when the incidence graph of the hypergraph is planar

Volume Segmentation of 3-dimensional Images

We present a practical method to segment large medical images that takes the whole 3-dimensional structure into account. We use a Union-Find data structure to record and maintain the necessary information during the segmentation process. Due to the large data size, we are forced to divide our process in two parts: a "weak segmentation" of the individual sections and a global integration of all the data. This method shows good results on computer tomographies

The Role of Synthetic Geometry in Representational Measurement Theory

Geometric representations of data and the formulation of quantitative models of observed phenomena are of main interest in all kinds of empirical sciences. To support the formulation of quantitative models, {\it representational measurement theory} studies the foundations of measurement. By mathematical methods it is analysed under which conditions attributes have numerical measurements and which numerical manipulations of the measurement values are meaningful (see Krantz et al.~(1971)). In this paper, we suggest to discuss within the measurement theory approach both, the idea of geometric representations of data and the request to provide algebraic descriptions of dependencies of attributes. We show that, within such a broader paradigm of representational measurement theory, synthetic geometry can play a twofold role which enriches the theory and the possibilities of data interpretation

Memory Management for Union-Find Algorithms

We provide a general tool to improve the real time performance of a broad class of Union-Find algorithms. This is done by minimizing the random access memory that is used and thus to avoid the well-known von~Neumann bottleneck of synchronizing CPU and memory. A main application to image segmentation algorithms is demonstrated where the real time performance is drastically improved

Who witnesses The Witness? Finding witnesses in The Witness is hard and sometimes impossible

We analyze the computational complexity of the many types of pencil-and-paper-style puzzles featured in the 2016 puzzle video game The Witness. In all puzzles, the goal is to draw a simple path in a rectangular grid graph from a start vertex to a destination vertex. The different puzzle types place different constraints on the path: preventing some edges from being visited (broken edges); forcing some edges or vertices to be visited (hexagons); forcing some cells to have certain numbers of incident path edges (triangles); or forcing the regions formed by the path to be partially monochromatic (squares), have exactly two special cells (stars), or be singly covered by given shapes (polyominoes) and/or negatively counting shapes (antipolyominoes). We show that any one of these clue types (except the first) is enough to make path finding NP-complete ("witnesses exist but are hard to find"), even for rectangular boards. Furthermore, we show that a final clue type (antibody), which necessarily "cancels" the effect of another clue in the same region, makes path finding $\Sigma_2$-complete ("witnesses do not exist"), even with a single antibody (combined with many anti/polyominoes), and the problem gets no harder with many antibodies. On the positive side, we give a polynomial-time algorithm for monomino clues, by reducing to hexagon clues on the boundary of the puzzle, even in the presence of broken edges, and solving "subset Hamiltonian path" for terminals on the boundary of an embedded planar graph in polynomial time.Comment: 72 pages, 59 figures. Revised proof of Lemma 3.5. A short version of this paper appeared at the 9th International Conference on Fun with Algorithms (FUN 2018

Algorithms for DFM in electronic design automation

As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit of physics at the expense of design flexibility. On the other hand, IC designs inevitably becomes more complex to meet the increasing demand of computational power. To close this gap, design for manufacturing (DFM) becomes the key to enable an easy and low-cost IC fabrication. Therefore, efficient electronic design automation (EDA) algorithms must be developed for DFM to address the design constraints and help the designers to better facilitate the manufacture process. As the core of manufacturing ICs, conventional lithography systems (193i) reach their limit for the 22 nm technology node and beyond. Consequently, several advanced lithography techniques are proposed, such as multiple patterning lithography (MPL), extreme ultra-violet lithography (EUV), electron beam (E-beam), and block copolymer directed self-assembly (DSA); however, DFM algorithms are essential for them to achieve better printability of a design. In this dissertation, we focus on analyzing the compatibility of designs and various advanced lithography techniques, and develop efficient algorithms to enable the manufacturing. We first explore E-Beam, one of the promising candidates for IC fabrication beyond the 10 nm technology node. To address its low throughput issue, the character projection technique has been proposed, and its stencil planning can be optimized with an awareness of overlapping characters. 2D stencil planning is proved NP-Hard. With the assumption of standard cells, the 2D problem can be partitioned into 1D row ordering subproblems; however, it is also considered hard, and no efficient optimal solution has been provided so far. We propose a polynomial time optimal algorithm to solve the 1D row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Technical proofs and experimental results verify that our algorithm is efficient and indeed optimal. As the most popular and practical lithography technique, MPL utilizes multiple exposures to print a single layout and thus allows placement of features within the minimum distance. Therefore, a feasible decomposition of the layout is a must to adopt MPL, and it is usually formulated as a graph k-coloring problem, which is computationally difficult for k > 2. We study the k-colorability of rectangular and diagonal grid graphs as induced subgraphs of a rectangular or diagonal grid respectively, since it has direct applications in printing contact/via layouts. It remains an open question on how hard it is to color grid graphs due to their regularity and sparsity. In this dissertation, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm for those graphs and conduct experiments to verify its performance and effectiveness. Besides, we also develop an efficient algorithm for model based MPL, because it is more expensive but accurate than the rule based decomposition. As one of the alternative lithography techniques, block copolymer directed self-assembly (DSA) is studied. It has emerged as a low-cost, high- throughput option in the pursuit of alternatives to traditional optical lithography. However, issues of defectivity have hampered DSA’s viability for large-scale patterning. Recent studies have shown the copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density has been demonstrated. In this dissertation, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. We also apply our knowledge in coloring grid graphs to the problem of group-and-coloring in DSA-MPL hybrid lithography. We derive a solution to group-3-coloring and prove the NP-completeness of grouping-2-coloring

Drawing Graphs on Rectangular Grids with at most 2 Bends per Edge

Given an undirected graph G = (V; E) with n vertices of maximum degree 4. It is well known that such a graph can be embedded in a rectangular grid with at most 2n columns and 2n rows such that any edge is embedded with at most 5 bends. On the other hand, two is a lower bound on the maximum number of bends per embedded edge since the graph K 5 cannot be embedded with less than 2 bends per embedded edge. We present an algorithm that computes an embedding for arbitrary graphs with n vertices of maximum degree 4 in a grid with exactly 2n columns and 2n rows such that all edges are embedded with at most 2 bends per edge. 1 Introduction Building layouts of integrated circuits on chips is quite difficult. The larger the area covered by a circuit, the more difficult is the production of trouble--free chips. Thus, minimizing the area covered by a circuit is a natural effort in VLSI--Design. In practice, other parameters play a role as well: the lengths of the wire (total sum or maximum length)..