2,181 research outputs found

    Design of Energy-Efficient Approximate Arithmetic Circuits

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    Energy consumption has become one of the most critical design challenges in integrated circuit design. Arithmetic computing circuits, in particular array-based arithmetic computing circuits such as adders, multipliers, squarers, have been widely used. In many cases, array-based arithmetic computing circuits consume a significant amount of energy in a chip design. Hence, reduction of energy consumption of array-based arithmetic computing circuits is an important design consideration. To this end, designing low-power arithmetic circuits by intelligently trading off processing precision for energy saving in error-resilient applications such as DSP, machine learning and neuromorphic circuits provides a promising solution to the energy dissipation challenge of such systems. To solve the chip’s energy problem, especially for those applications with inherent error resilience, array-based approximate arithmetic computing (AAAC) circuits that produce errors while having improved energy efficiency have been proposed. Specifically, a number of approximate adders, multipliers and squarers have been presented in the literature. However, the chief limitation of these designs is their un-optimized processing accuracy, which is largely due to the current lack of systemic guidance for array-based AAAC circuit design pertaining to optimal tradeoffs between error, energy and area overhead. Therefore, in this research, our first contribution is to propose a general model for approximate array-based approximate arithmetic computing to guide the minimization of processing error. As part of this model, the Error Compensation Unit (ECU) is identified as a key building block for a wide range of AAAC circuits. We develop theoretical analysis geared towards addressing two critical design problems of the ECU, namely, determination of optimal error compensation values and identification of the optimal error compensation scheme. We demonstrate how this general AAAC model can be leveraged to derive practical design insights that may lead to optimal tradeoffs between accuracy, energy dissipation and area overhead. To further minimize energy consumption, delay and area of AAAC circuits, we perform ECU logic simplification by introducing don't cares. By applying the proposed model, we propose an approximate 16x16 fixed-width Booth multiplier that consumes 44.85% and 28.33% less energy and area compared with theoretically the most accurate fixed-width Booth multiplier when implemented using a 90nm CMOS standard cell library. Furthermore, it reduces average error, max error and mean square error by 11.11%, 28.11% and 25.00%, respectively, when compared with the best reported approximate Booth multiplier and outperforms the best reported approximate design significantly by 19.10% in terms of the energy-delay-mean square error product (EDE_(ms)). Using the same approach, significant energy consumption, area and error reduction is achieved for a squarer unit, with more than 20.00% EDE_(ms) reduction over existing fixed-width squarer designs. To further reduce error and cost by utilizing extra signatures and don't cares, we demonstrate a 16-bit fixed-width squarer that improves the energy-delay-max error (EDE_(max)) by 15.81%

    JPEG-like Image Compression using Neural-network-based Block Classification and Adaptive Reordering of Transform Coefficients

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    The research described in this thesis addresses aspects of coding of discrete-cosinetransform (DCT) coefficients, that are present in a variety of transform-based digital-image-compression schemes such as JPEG. Coefficient reordering; that directly affects the symbol statistics for entropy coding, and therefore the effectiveness of entropy coding; is investigated. Adaptive zigzag reordering, a novel versatile technique that achieves efficient reordering by processing variable-size rectangular sub-blocks of coefficients, is developed. Classification of blocks of DCT coefficients using an artificial neural network (ANN) prior to adaptive zigzag reordering is also considered. Some established digital-image-compression techniques are reviewed, and the JPEG standard for the DCT-based method is studied in more detail. An introduction to artificial neural networks is provided. Lossless conversion of blocks of coefficients using adaptive zigzag reordering is investigated, and experimental results are presented. A versatile algorithm, that generates zigzag scan paths for sub-blocks of any dimensions using a binary decision tree, is developed. An implementation of the algorithm based on programmable logic devices (PLDs) is described demonstrating the feasibility of hardware implementations. Coding of the sub-block dimensions, that need to be retained in order to reconstruct a sub-block during decoding, based on the scan-path length is developed. Lossy conversion of blocks of coefficients is also considered, and experimental results are presented. A two-layer feedforward artificial neural network trained using an error-backpropagation algorithm, that determines the sub-block dimensions, is described. Isolated nonzero coefficients of small significance are discarded in some blocks, and therefore smaller sub-blocks are generated

    Digital encoding of black and white facsimile signals

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    As the costs of digital signal processing and memory hardware are decreasing each year compared to those of transmission, it is increasingly economical to apply sophisticated source encoding techniques to reduce the transmission time for facsimile documents. With this intent, information lossy encoding schemes have been investigated in which the encoder is divided into two stages. Firstly, preprocessing, which removes redundant information from the original documents, and secondly, actual encoding of the preprocessed documents. [Continues.

    Entropy of delta-coded speech

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    Proceedings: Voice Technology for Interactive Real-Time Command/Control Systems Application

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    Speech understanding among researchers and managers, current developments in voice technology, and an exchange of information concerning government voice technology efforts are discussed

    Voice over IP

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    The area that this thesis covers is Voice over IP (or IP Telephony as it is sometimes called) over Private networks and not over the Internet. There is a distinction to be made between the two even though the term is loosely applied to both. IP Telephony over Private Networks involve calls made over private WANs using IP telephony protocols while IP Telephony over the Internet involve calls made over the public Internet using IP telephony protocols. Since the network is private, service is reliable because the network owner can control how resources are allocated to various applications, such as telephony services. The public Internet on the other hand is a public, largely unmanaged network that offers no reliable service guarantee. Calls placed over the Internet can be low in quality, but given the low price, some find this solution attractive. What started off as an Internet Revolution with free phone calls being offered to the general public using their multimedia computers has turned into a telecommunication revolution where enterprises are beginning to converge their data and voice networks into one network. In retrospect, an enterprise\u27s data networks are being leveraged for telephony. The communication industry has come full circle. Earlier in the decade data was being transmitted over the public voice networks and now voice is just another application which is/will be run over the enterprises existing data networks. We shall see in this thesis the problems that are encountered while sending Voice over Data networks using the underlying IP Protocol and the corrective steps taken by the Industry to resolve these multitudes of issues. Paul M. Zam who is collaborating in this Joint Thesis/project on VoIP will substantiate this theoretical research with his practical findings. On reading this paper the reader will gain an insight in the issues revolving the implementation of VoIP in an enterprises private network as well the technical data, which sheds more light on the same. Thus the premise of this joint thesis/project is to analyze the current status of the technology and present a business case scenario where an organization will be able to use this information
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