Engineering studies related to geodetic and oceanographic remote sensing using short pulse techniques

For the Skylab S-193 radar altimeter, data processing flow charts and identification of calibration requirements and problem areas for defined S-193 altimeter experiments are presented. An analysis and simulation of the relationship between one particular S-193 measurement and the parameter of interest for determining the sea surface scattering cross-section are considered. For the GEOS-C radar altimeter, results are presented for system analyses pertaining to signal-to-noise ratio, pulse compression threshold behavior, altimeter measurement variance characteristics, desirability of onboard averaging, tracker bandwidth considerations, and statistical character of the altimeter data in relation to harmonic analysis properties of the geodetic signal

Design study of a low cost civil aviation GPS receiver system

A low cost Navstar receiver system for civil aviation applications was defined. User objectives and constraints were established. Alternative navigation processing design trades were evaluated. Receiver hardware was synthesized by comparing technology projections with various candidate system designs. A control display unit design was recommended as the result of field test experience with Phase I GPS sets and a review of special human factors for general aviation users. Areas requiring technology development to ensure a low cost Navstar Set in the 1985 timeframe were identified

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio

Smart and high-performance digital-to-analog converters with dynamic-mismatch mapping

The trends of advanced communication systems, such as the high data rate in multi-channel base-stations and digital IF conversion in software-defined radios, have caused a continuously increasing demand for high performance interface circuits between the analog and the digital domain. A Digital-to-Analog converter (DAC) is such an interface circuit in the transmitter path. High bandwidth, high linearity and low noise are the main design challenges in high performance DACs. Current-steering is the most suitable architecture to meet these performance requirements. The aim of this thesis is to develop design techniques for high-speed high-performance Nyquist current-steering DACs, especially for the design of DACs with high dynamic performance, e.g. high linearity and low noise. The thesis starts with an introduction to DACs in chapter 2. The function in time/frequency domain, performance specifications, architectures and physical implementations of DACs are brie y discussed. Benchmarks of state-of-the-art published Nyquist DACs are also given. Chapter 3 analyzes performance limitations by various error sources in Nyquist current-steering DACs. The outcome shows that in the frequency range of DC to hundreds of MHz, mismatch errors, i.e. amplitude and timing errors, dominate the DAC linearity. Moreover, as frequencies increase, the effect of timing errors becomes more and more dominant over that of amplitude errors. Two new parameters, i.e. dynamic-INL and dynamic-DNL, are proposed to evaluate the matching of current cells. Compared to the traditional static-INL/DNL, the dynamic-INL/DNL can describe the matching between current cells more accurately and completely. By reducing the dynamic-INL/DNL, the non-linearities caused by all mismatch errors can be reduced. Therefore, both the DAC static and dynamic performance can be improved. The dynamic-INL/DNL are frequency-dependent parameters based on the measurement modulation frequency fm. This fm determines the weight between amplitude and timing errors in the dynamic-INL/DNL. Actually, this gives a freedom to optimize the DAC performance for different applications, e.g. low fm for low frequency applications and high fm for high frequency applications. Chapter 4 summarizes the existing design techniques for intrinsic and smart DACs. Due to technology limitations, it is diffcult to reduce the mismatch errors just by intrinsic DAC design with reasonable chip area and power consumption. Therefore, calibration techniques are required. An intrinsic DAC with calibration is called a smart DAC. Existing analog calibration techniques mainly focus on current source calibration, so that the amplitude error can be reduced. Dynamic element matching is a kind of digital calibration technique. It can reduce the non-linearities caused by all mismatch errors, but at the cost of an increased noise oor. Mapping is another kind of digital calibration technique and will not increase the noise. Mapping, as a highly digitized calibration technique, has many advantages. Since it corrects the error effects in the digital domain, the DAC analog core can be made clean and compact, which reduces the parasitics and the interference generated in the analog part. Traditional mapping is static-mismatch mapping, i.e. mapping only for amplitude errors, which many publications have already addressed on. Several concepts have also been proposed on mapping for timing errors. However, just mapping for amplitude or timing error is not enough to guarantee a good performance. This work focuses on developing mapping techniques which can correct both amplitude and timing errors at the same time. Chapter 5 introduces a novel mapping technique, called dynamic-mismatch mapping (DMM). By modulating current cells as square-wave outputs and measuring the dynamic-mismatch errors as vectors, DMM optimizes the switching sequence of current cells based on dynamic-mismatch error cancelation such that the dynamic-INL can be reduced. After reducing the dynamic-INL, the non-linearities caused by both amplitude and timing errors can be significantly reduced in the whole Nyquist band, which is confirmed by Matlab behavioral-level Monte-Carlo simulations. Compared to traditional static-mismatch mapping (SMM), DMM can reduce the non-linearities caused by both amplitude and timing errors. Compared to dynamic element matching (DEM), DMM does not increase the noise floor. The dynamic-mismatch error has to be accurately measured in order to gain the maximal benefit from DMM. An on-chip dynamic-mismatch error sensor based on a zero-IF receiver is proposed in chapter 6. This sensor is especially designed for low 1/f noise since the signal is directly down-converted to DC. Its signal transfer function and noise analysis are also given and con??rmed by transistor-level simulations. Chapter 7 gives a design example of a 14-bit current-steering DAC in 0.14mum CMOS technology. The DAC can be configured in an intrinsic-DAC mode or a smart-DAC mode. In the intrinsic-DAC mode, the 14-bit 650MS/s intrinsic DAC core achieves a performance of SFDR>65dBc across the whole 325MHz Nyquist band. In the smart-DAC mode, compared to the intrinsic DAC performance, DMM improves the DAC performance in the whole Nyquist band, providing at least 5dB linearity improvement at 200MS/s and without increasing the noise oor. This 14-bit 200MS/s smart DAC with DMM achieves a performance of SFDR>78dBc, IM

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Machine Learning Techniques To Mitigate Nonlinear Impairments In Optical Fiber System

The upcoming deployment of 5/6G networks, online services like 4k/8k HDTV (streamers and online games), the development of the Internet of Things concept, connecting billions of active devices, as well as the high-speed optical access networks, impose progressively higher and higher requirements on the underlying optical networks infrastructure. With current network infrastructures approaching almost unsustainable levels of bandwidth utilization/ data traffic rates, and the electrical power consumption of communications systems becoming a serious concern in view of our achieving the global carbon footprint targets, network operators and system suppliers are now looking for ways to respond to these demands while also maximizing the returns of their investments. The search for a solution to this predicted ªcapacity crunchº led to a renewed interest in alternative approaches to system design, including the usage of high-order modulation formats and high symbol rates, enabled by coherent detection, development of wideband transmission tools, new fiber types (such as multi-mode and ±core), and finally, the implementation of advanced digital signal processing (DSP) elements to mitigate optical channel nonlinearities and improve the received SNR. All aforementioned options are intended to boost the available optical systems’ capacity to fulfill the new traffic demands. This thesis focuses on the last of these possible solutions to the ªcapacity crunch," answering the question: ªHow can machine learning improve existing optical communications by minimizing quality penalties introduced by transceiver components and fiber media nonlinearity?". Ultimately, by identifying a proper machine learning solution (or a bevy of solutions) to act as a nonlinear channel equalizer for optical transmissions, we can improve the system’s throughput and even reduce the signal processing complexity, which means we can transmit more using the already built optical infrastructure. This problem was broken into four parts in this thesis: i) the development of new machine learning architectures to achieve appealing levels of performance; ii) the correct assessment of computational complexity and hardware realization; iii) the application of AI techniques to achieve fast reconfigurable solutions; iv) the creation of a theoretical foundation with studies demonstrating the caveats and pitfalls of machine learning methods used for optical channel equalization. Common measures such as bit error rate, quality factor, and mutual information are considered in scrutinizing the systems studied in this thesis. Based on simulation and experimental results, we conclude that neural network-based equalization can, in fact, improve the channel quality of transmission and at the same time have computational complexity close to other classic DSP algorithms

Space station tracking requirements feasibility study, volume 1

The objective of this feasibility study is to determine analytically the accuracies of various sensors being considered as candidates for Space Station use. Specifically, the studies were performed whether or not the candidate sensors are capable of providing the required accuracy, or if alternate sensor approaches be investigated. Other topics related to operation in the Space Station environment were considered as directed by NASA-JCS. The following topics are addressed: (1) Space Station GPS; (2) Space Station Radar; (3) Docking Sensors; (4) Space Station Link Analysis; (5) Antenna Switching, Power Control, and AGC Functions for Multiple Access; (6) Multichannel Modems; (7) FTS/EVA Emergency Shutdown; (8) Space Station Information Systems Coding; (9) Wanderer Study; and (10) Optical Communications System Analysis. Brief overviews of the abovementioned topics are given. Wherever applicable, the appropriate appendices provide detailed technical analysis. The report is presented in two volumes. This is Volume 1, containing the main body and Appendices A through J

Advanced Modulation and Coding Technology Conference

The objectives, approach, and status of all current LeRC-sponsored industry contracts and university grants are presented. The following topics are covered: (1) the LeRC Space Communications Program, and Advanced Modulation and Coding Projects; (2) the status of four contracts for development of proof-of-concept modems; (3) modulation and coding work done under three university grants, two small business innovation research contracts, and two demonstration model hardware development contracts; and (4) technology needs and opportunities for future missions

High-speed flash adc design

Master'sMASTER OF ENGINEERIN

Advanced raman amplification techniques for high capacity and broadband coherent optical transmission systems

This thesis presents a detailed study of different advanced Raman fibre laser (RFL) based amplification schemes and the development of novel broadband distributed and discrete Raman amplifiers in order to improve the transmission performance of modern high capacity, long-haul coherent optical systems. The numerical modelling of different Raman amplifier techniques including power distribution of signal, pump and noise components, RIN transfer from pump to signal, broadband gain optimization and so on have been described in details.The RIN and noise performances of RFL based distributed Raman amplifiers (DRAs) with different span lengths, forward pump powers and input reflection levels have been characterized experimentally. It has been shown through coherent transmission experiment that, in order to improve pump power efficiency, a low level of input reflection up to ~10% can be allowed without increasing the Q factor penalty > 1dB due to additional signal RIN penalty.A novel broadband (>10nm) first order Raman pump is developed for use as a forward pump in long-haul transmission experiment. Significant signal RIN mitigation up to 10dB compared with conventional low RIN, narrowband sources was obtained for bidirectional DRA schemes. Long-haul coherent transmission experiments with 10×120Gb/s DP-QPSK system were carried out in are circulating loop setup using the proposed broadband pump in bidirectional and backward only pumping configurations. The maximum transmission reach up to ~8330km was reported with first order broadband pumped bidirectional DRA, with transmission reach extensions of 1250km and1667km compared with conventional backward only and first order semiconductor pumped bidirectional pumping scheme respectively.Finally, a novel design of bidirectional broadband distributed DRA is proposed to reduce the noise figure tilt and improve the WDM transmission performances. Furthermore, broadband discrete Raman amplifier schemes in dual stage configuration are also shown for high gain, high output power, low noise and low nonlinear performance