Study of substrate noise and techniques for minimization

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 155-158).This thesis presents a study of the effects of substrate noise on analog circuits in mixed-signal chips and techniques for minimizing these harmful effects on sensitive analog circuits. A microchip built in a 0.25um CMOS epitaxial process was designed, fabricated, and tested for this research. Through the use of an on-chip sampling scope, the effect of substrate noise generated by digital inverters with coupling capacitors to the substrate on analog circuits was characterized. Substrate noise coupled into a representative analog circuit, a switched capacitor delta-sigma modulator primarily through the asymmetrical parasitics of the input sampling circuit. Furthermore, since some of the parasitics are nonlinear with input voltage, substrate noise couples into the analog circuits producing an input signal dependent component and an input signal independent component. The substrate noise, with decay time constants of a few nanoseconds and ringing frequencies of few hundred megahertz, can decrease analog circuit performance. In the case of a delta-sigma modulator, substrate noise caused the signal to noise power ratio to decrease by more than 18dB, 3 bits in terms of analog-to-digital converter metrics. In addition, two techniques of minimizing the substrate noise and its effects were explored. The first used a replica delta-sigma modulator on the same chip to subtract the effects of substrate noise from the original delta-sigma modulator. This method proved useful for removing input signal independent substrate noise, but not input signal dependent substrate noise which dominates in-band noise for large input signal magnitudes. The second technique involved an active substrate noise cancellation system.(cont.) A discrete time feedback loop senses the substrate noise, processes it through a filter, and uses an array of digital inverters to cancel the substrate noise. The principal advantages of this technique are the shaping of substrate noise through a designed filter without a significant power penalty and design independence from the analog and digital components. Measured data shows that this technique is capable of over 20dB reduction in substrate noise on the substrate voltage itself. Measured data also shows over 10dB improvement in SNDR of the delta-sigma modulator in certain cases.by Mark Shane Peng.Ph.D

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

An Evaluation of the S2Ia switched-current architecture for (delta)(sigma) modulator ADCs

Switched-Current (SI) is a design methodology by which discrete time, current mode, analog circuits can be implemented using standard digital CMOS processes, allowing the addition of analog signal processing circuits, analog to digital converters (ADCs), digital to analog converters (DACs) and other analog and mixed-signal circuits to otherwise digital only microchips without the need and expense of any extra fabrication steps. SI circuits operate by employing a secondary effect in CMOS circuits, a transistor\u27s gate capacitance, to store charge and thus form a current memory cell. A current memory cell is one of the basic building blocks found in most SI circuits and is usually the distinguishing feature of the various approaches to SI circuit design. Delta Sigma Modulators (DSMs) are discrete time, mixed-signal circuits making them well suited to implementation using the SI methodology. These circuits can form the basis of either an ADC or DAC and thus provide a good example of the SI technique employing a particular current memory cell implementation. For this work, a First Order DSM-based ADC was designed and simulated to verify the feasibility of a variant of the S2I Switched-Current Memory Cell architecture, the S2Ia Switched-Current Memory Cell, in a low-voltage, digital, 0.5/j.m CMOS process. The A D C design was targeted towards voiceband (4kHz bandwidth) applications over which it achieved a 6-bit resolution and separately attained a greater than 80kHz bandwidth. Extension of the First Order DSM employed in this design to a Second Order DSM would increase the resolution to at least 8-bits without sacrificing bandwidth. Although potentially less accurate than the S2I Switched-Current Memory Cell, a S2Ia cell has the advantage of requiring only two clock signals to the S2I cell\u27s four. Further, for cascades of S2Ia cells the number of clock signals remains two while a S2I cell cascade requires six separate clock signals. S2Ia-based circuits therefore require less complex clock generation circuitry and fewer clock lines

Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

Variable Spurious Noise Mitigation Techniques in Hysteretic Buck Converters

This work proposes a current-mode hysteretic buck converter with a spur-free constant-cycle frequency-hopping controller that fully eliminates spurs from the switching noise spectrum irrespective of variations in the switching frequency and operating conditions. As a result, the need for frequency regulation loops to ensure non-varying switching frequency (i.e. fixed spurs location) in hysteretic controllers is eliminated. Moreover, compared to frequency regulation loops, the proposed converter offers the advantage of eliminating mixing and interference altogether due to its spur-free operation, and thus, it can be used to power, or to be integrated within noise-sensitive systems while benefiting from the superior dynamic performance of its hysteretic operation. The proposed converter uses dual-sided hysteretic band modulation to eliminate the inductor current imbalance that results from frequency hopping along with the output voltage transients and low-frequency noise floor peaking associated with it. Moreover, a feedforward adaptive hysteretic band controller is proposed to reduce variations in the switching frequency with the input voltage, and an all-digital soft-startup circuit is proposed to control the in-rush current without requiring any off-chip components. The converter is implemented in a 0.35-õm standard CMOS technology and it achieves 92% peak efficiency

Sigma-Delta control of charge trapping in heterogeneous devices

Dielectric charging represents a major reliability issue in a variety of semiconductor devices. The accumulation of charge in dielectric layers of a device often alters its performance, affecting its circuital features and even reducing its effective lifetime. Although several contributions have been made in order to mitigate the undesired effects of charge trapping on circuit performance, dielectric charge trapping still remains an open reliability issue in several applications. The research work underlying this Thesis mainly focuses on the design, analysis and experimental validation of control strategies to compensate dielectric charging in heterogeneous devices. These control methods are based on the application of specifically designed voltage waveforms that produce complementary effects on the charge dynamics. Using sigma-delta loops, these controls allow to set and maintain, within some limits, the net trapped charge in the dielectric to desired levels that can be changed with time. This allows mitigating long-term reliability issues such as capacitance-voltage (C-V) shifts in MOS and MIM capacitors. Additionally, the bit streams generated by the control loops provide real-time information on the evolution of the trapped charge. The proposed controls also allow compensating the effects of the charge trapping due to external disturbances such as radiation. This has been demonstrated experimentally with MOS capacitors subjected to various types of ionizing radiation (X-rays and gamma rays) while a charge control is being applied. This approach opens up the possibility of establishing techniques for active compensation of radiation-induced charge in MOS structures as well as a new strategy for radiation sensing. A modeling strategy to characterize the dynamics of the dielectric charge in MOS capacitors is also presented. The diffusive nature of the charge trapping phenomena allows their behavioral characterization using Diffusive Representation tools. The experiments carried out demonstrate a very good matching between the predictions of the model and the experimental results obtained. The time variations in the charge dynamics due to changes in the volatges applied and/or due to external disturbances have been also investigated and modeled. Moreover, the charge dynamics of MOS capacitors under sigma-delta control is analyzed using the tools of Sliding Mode Controllers for an infinite sampling frequency approximation. A phenomenological analytical model is obtained which allows to predict and analyze the sequence of control signals. This model has been successfully validated with experimental data. Finally, the above control strategies are extended to other devices such as eMIM capacitors and perovskite solar cells. Preliminary results including open loop and closed loop control experiments are presented. These results demonstrate that the application of the controls allows to set and stabilize both the C-V characteristic of an eMIM capacitor and the current-voltage characteristic (J-V) of a perovskite solar cell.La carga atrapada en dieléctricos suele implicar un problema importante de fiabilidad en muchos dispositivos semiconductores. La acumulación de dicha carga, normalmente provocada por las tensiones aplicadas durante el uso del dispositivo, suele alterar el rendimiento de éste con el tiempo, afectar sus prestaciones a nivel de circuital e, incluso, reducir su vida útil. Aunque durante años se han realizado muchos trabajos para mitigar sus efectos no deseados, sobre todo a nivel circuital, la carga atrapada en dieléctricos sigue siendo un problema abierto que frena la aplicabilidad práctica de algunos dispositivos. El trabajo de investigación realizado en esta Tesis se centra principalmente en el diseño, análisis y validación experimental de estrategias de control para compensar la carga atrapada en dieléctricos de diversos tipos de dispositivos, incluyendo condensadores MOS, condensadores MIM fabricados con nanotecnología y dispositivos basados en perovskitas. Los controles propuestos se basan en utilizar formas de onda de tensión, específicamente diseñadas, que producen efectos complementarios en la dinámica de la carga. Mediante el uso de lazos sigma-delta, estos controles permiten establecer y mantener, dentro de unos límites, la carga neta atrapada en el dieléctrico a valores prefijados, que pueden cambiarse con el tiempo. Esto permite mitigar problemas de fiabilidad a largo plazo como por ejemplo las derivas de la curva capacidad-tensión (C-V) en condensadores MOS y MIM. Adicionalmente, las tramas de bits generadas por los lazos de control proporcionan información en tiempo real sobre la evolución de la carga. Los controles propuestos permiten también compensar los efectos de la carga atrapada en dieléctricos debida a perturbaciones externas como la radiación. Esto se ha demostrado experimentalmente con condesadores MOS sometidos a diversos tipos de radiación ionizante (rayos X y gamma) mientras se les aplicaba un control de carga. Este resultado abre la posibilidad tanto de establecer técnicas de compensación activa de carga inducida por radiación en estructuras MOS, como una nueva estrategia de sensado de radiación. Se presenta también una estrategia de modelado para caracterizar la dinámica de la carga dieléctrica en condensadores MOS. La naturaleza difusiva de los fenómenos de captura y eliminación de carga en dieléctricos permite caracterizar dichos fenómenos empleando herramientas de Representación Difusiva. Los experimentos realizados demuestran una muy buena correspondencia entre las predicciones del modelo y los resultados experimentales obtenidos. Se muestra también como las variaciones temporales de los modelos son debidas a cambios en las formas de onda de actuación del dispositivo y/o a perturbaciones externas. Además, la dinámica de carga en condensadores MOS bajo control sigma-delta se analiza utilizando herramientas de control en modo deslizante (SMC), considerando la aproximación de frecuencia de muestreo infinita. Con ello se obtiene un modelo analítico simplificado que permite predecir y analizar con éxito la secuencia de señales de control. Este modelo se ha validado satisfactoriamente con datos experimentales. Finalmente, las estrategias de control anteriores se han extendido a otros dispositivos susceptibles de sufrir efectos de carga atrapada que pueden afectar su fiabilidad. Así, se han llevado a cabo experimentos preliminares cuyos resultados demuestran que la aplicación de controles de carga permite controlar y estabilizar la característica C-V de un condensador eMIM y la característica corriente-tensión (J-V) de una célula solar basada en perovskitas.Postprint (published version