Switched-Current (SI) is a design methodology by which discrete time, current mode, analog circuits can be implemented using standard digital CMOS processes, allowing the addition of analog signal processing circuits, analog to digital converters (ADCs), digital to analog converters (DACs) and other analog and mixed-signal circuits to otherwise digital only microchips without the need and expense of any extra fabrication steps. SI circuits operate by employing a secondary effect in CMOS circuits, a transistor\u27s gate capacitance, to store charge and thus form a current memory cell. A current memory cell is one of the basic building blocks found in most SI circuits and is usually the distinguishing feature of the various approaches to SI circuit design. Delta Sigma Modulators (DSMs) are discrete time, mixed-signal circuits making them well suited to implementation using the SI methodology. These circuits can form the basis of either an ADC or DAC and thus provide a good example of the SI technique employing a particular current memory cell implementation. For this work, a First Order DSM-based ADC was designed and simulated to verify the feasibility of a variant of the S2I Switched-Current Memory Cell architecture, the S2Ia Switched-Current Memory Cell, in a low-voltage, digital, 0.5/j.m CMOS process. The A D C design was targeted towards voiceband (4kHz bandwidth) applications over which it achieved a 6-bit resolution and separately attained a greater than 80kHz bandwidth. Extension of the First Order DSM employed in this design to a Second Order DSM would increase the resolution to at least 8-bits without sacrificing bandwidth. Although potentially less accurate than the S2I Switched-Current Memory Cell, a S2Ia cell has the advantage of requiring only two clock signals to the S2I cell\u27s four. Further, for cascades of S2Ia cells the number of clock signals remains two while a S2I cell cascade requires six separate clock signals. S2Ia-based circuits therefore require less complex clock generation circuitry and fewer clock lines
