Self-interference cancellation enabling high-throughput short-reach wireless full-duplex communication

In-band full-duplex (FD) wireless communication allows the simultaneous transmission and reception of data at the same frequency band, effectively doubling the spectral efficiency and data rate while reducing the latency. Previously published designs mostly target the self-interference (SI) cancellation in conventional wireless systems. In this paper, we focus on real-time SI cancellation for short-reach wireless FD systems. The superior signal quality of a point-to-point short-reach wireless system, allows the utilization of wideband communications to achieve a high throughput. Besides, in such wireless systems, the impacts of phase noise and nonlinear distortions are largely reduced, easing the SI cancellation. Moreover, the degradation of signal reception quality due to FD operation is experimentally evaluated in different environments. Experimental results of a prototype implementation show that a combination of antenna isolation and digital cancellation can already achieve an overall SI cancellation performance of 72.5 dB over a bandwidth of 123 MHz. This prototype can support a high-data-rate FD communication link of close to 1 Gbps up to 300 cm with an error vector magnitude lower than -26 dB in a typical indoor environment

Analog Cancellation of a Known Remote Interference: Hardware Realization and Analysis

The onset of quantum computing threatens commonly used schemes for information secrecy across wireless communication channels, particularly key-based data-level encryption. This calls for secrecy schemes that can provide everlasting secrecy resistant to increased computational power of an adversary. One novel physical layer scheme proposes that an intended receiver capable of performing analog cancellation of a known key-based interference would hold a significant advantage in recovering small underlying messages versus an eavesdropper performing cancellation after analog-to-digital conversion. This advantage holds even in the event that an eavesdropper can recover and use the original key in their digital cancellation. Inspired by this scheme, a flexible software-defined radio receiver design capable of maintaining analog cancellation ratios consistently over 40 dB, reaching up to and over 50 dB, is implemented in this thesis. Maintaining this analog cancellation requires very precise time-frequency synchronization along with accurate modeling and simulation of the channel effects on the interference. The key sources of synchronization error preventing this test bed from achieving and maintaining perfect interference cancellation, sub-sample period timing errors and limited radio frequency stability, are explored for possible improvements. To further prove robustness of the implemented secrecy scheme, the testbed is shown to operate with both phase-shift keying and frequency-modulated waveforms. Differences in the synchronization algorithm used for the two waveforms are highlighted. Interference cancellation performance is measured for increasing interference bandwidth and shown to decrease with such. The implications this testbed has on security approaches based on intentional interference employed to confuse eavesdroppers is approached from the framework proposed in the motivating everlasting secrecy scheme. Using analog cancellation levels from the hardware testbed, it is calculated that secrecy rates up to 2.3 bits/symbol are gained by receivers (intended or not) performing interference cancellation in analog rather than on a digital signal processor. Inspired by the positive gains in secrecy over systems not performing analog cancellation prior to signal reception, a novel secrecy scheme that focuses on the advantage an analog canceller holds in receiver amplifier compression is proposed here. The adversary amplifier is assumed to perform linear cancellation after the interference has passed through their nonlinear amplifier. This is accomplished by deriving the distribution of the interference residual after undergoing an inverse tangent transfer function and perfect linear cancellation. Parameters of this scheme are fit for the radios and cancellation ratios observed in the testbed, resulting in a secrecy gain of 0.95 bits/symbol. The model shows that larger message powers can still be kept secure for the achieved levels of cancellation, thus providing an even greater secrecy gain with increased message transmission power

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

Surpassing Fundamental Limits through Time Varying Electromagnetics

Surpassing the fundamental limits that govern all electromagnetic structures, such as reciprocity and the delay-bandwidth-size limit, will have a transformative impact on all applications based on electromagnetic circuits and systems. For instance, violating principles of reciprocity enables non-reciprocal components such as isolators and circulators, which find application in full-duplex wireless radios, radar, biomedical imaging, and quantum computing systems. Overcoming the delay-bandwidth-size limit enables ultra-broadband yet extremely-compact devices whose size is not fundamentally related to the wavelength at the operating frequency. The focus of this dissertation is on using time-variance as a new toolbox to overcome these fundamental limits and re-imagine circuit and system design. Traditional non-reciprocal components are realized using ferrite materials that loose their reciprocity under the application of external magnetic bias. However, the sheer volume, cost and weight of these magnet based non-reciprocal components coupled with their inability to be fabricated in conventional semiconductor processes, have limited their application to bulky and large-scale systems. Other approaches such as active-biased and non-linearity based non-reciprocity are compatible with semiconductor processes, however, they suffer from other poor linearity and noise performance. In this dissertation, using passive transistor switch as the modulating element, we have proposed the concept of spatio-temporal conductivity modulation and have demonstrated a gamut of non-reciprocal devices ranging from gyrators to isolators and circulators. Through novel circuit topologies, for the first time, we have demonstrated on-chip circulators with multi-watt input power handling, operation at high millimeter-wave frequencies, and tailor made circulators for emerging technologies such as simultaneous-transmit-and-receive MRI and quantum computing. Delay-bandwidth-size trade-off is another fundamental electromagnetic limit, that constrains the delay imparted by a medium or a device within a fixed footprint to be inversely proportional to the signal bandwidth. It is this limit that governs the size of any microwave passive devices to be inversely proportional to its operating frequency. As a part of this dissertation, through intelligent clocking of switched capacitor networks we overcame the delay-bandwidth-size limit, thus resulting in infinitesimal, yet broadband microwave devices. Here we proposed a new paradigm in wave propagation where the properties such as the propagation delay and characteristic impedance does not depend on the constituent elements/materials of the medium, but rather heavily rely on the user-defined modulation scheme, thereby opening huge opportunities for realizing highly-reconfigurable passives. Leveraging these concepts, we demonstrated wide range of reciprocal an non-reciprocal devices including ultra-compact delay elements, highly-reconfigurable microwave passives, ultra-wideband circulators with infinitesimal form-factors and dispersion-free chip scale floquet topological insulators. Application of these devices have also been evaluated in real-world systems through our demonstrations of wideband, full-duplex receivers leveraging switched capacitors based true-time-delay interference cancelers and floquet topological insulator based antenna interfaces for full-duplex phased-arrays and ultra-wideband beamformers. Furthermore, to cater the growing RF and microwave needs of future, large-scale quantum computing systems, we demonstrated a low-cryogenic, wideband circulator based on time modulation of superconducting devices. This superconducting circulator is expected to operate alongside the superconducting qubits, inside a dilution refrigerator at 10mK-100mK, thus enabling a tightly integrated quantum system. We also presented the design and implementation of a cryogenic-CMOS clock driver chip that will generate the clocks required by the superconducting circulator. Finally, we also demonstrated the design and implementation of a low-noise, low power consumption, 6GHz - 8GHz cryogenic downconversion receiver at 4K for cryogenic qubit readout

Distortion Reduction in Fractional Delay Filters

As the digital version of a continuous-time delay, the concept of fractional delay (FD) is exploited to approximate a desired delay that is not a multiple of the sampling interval. However, in FD filters, there is always a severe distortion at the beginning of delayed signals, referred to as head distortion. This letter identifies the cause of head distortion and proposes a solution to this problem for reducing the overall distortion in FD filters. For the purpose of performance evaluation, relative root-mean-square (RMS) error is formulated as a metric to quantify the overall difference between the frequency-domain response of an FD filter and the ideal one. Moreover, illustrative numerical results on the proposed scheme applied in FD filters with classical sinc, Farrow and Lagrange interpolation substantiate the validity and feasibility of our solution

Aperture-Level Simultaneous Transmit and Receive (STAR) with Digital Phased Arrays

In the signal processing community, it has long been assumed that transmitting and receiving useful signals at the same time in the same frequency band at the same physical location was impossible. A number of insights in antenna design, analog hardware, and digital signal processing have allowed researchers to achieve simultaneous transmit and receive (STAR) capability, sometimes also referred to as in-band full-duplex (IBFD). All STAR systems must mitigate the interference in the receive channel caused by the signals emitted by the system. This poses a significant challenge because of the immense disparity in the power of the transmitted and received signals. As an analogy, imagine a person that wanted to be able to hear a whisper from across the room while screaming at the top of their lungs. The sound of their own voice would completely drown out the whisper. Approaches to increasing the isolation between the transmit and receive channels of a system attempt to successively reduce the magnitude of the transmitted interference at various points in the received signal processing chain. Many researchers believe that STAR cannot be achieved practically without some combination of modified antennas, analog self-interference cancellation hardware, digital adaptive beamforming, and digital self-interference cancellation. The aperture-level simultaneous transmit and receive (ALSTAR) paradigm confronts that assumption by creating isolation between transmit and receive subarrays in a phased array using only digital adaptive transmit and receive beamforming and digital self-interference cancellation. This dissertation explores the boundaries of performance for the ALSTAR architecture both in terms of isolation and in terms of spatial imaging resolution. It also makes significant strides towards practical ALSTAR implementation by determining the performance capabilities and computational costs of an adaptive beamforming and self-interference cancellation implementation inspired by the mathematical structure of the isolation performance limits and designed for real-time operation

Co-channel Blocker and Self-Interferer Tolerant Receiver Architectures for MIMO and Full-Duplex MIMO Receivers

This research focuses on receiver architectures which enable better spectral e�ciency by handling blockers in the same spectral range as the signal. The presence of such blockers, without the use of blocker cancelling/�ltering techniques leads to gain compression and hence, consequent performance degradation of receivers leading to reduced spectrum e�ciency. Two approaches have been devised, implemented in silicon and measured to demonstrate that they alleviate the problems associated with blockers. A system capable of handling co-channel spatially separated blockers is implemented in the �rst work and another system capable of handling self-interference caused due to the transmitter during full-duplex operation constitutes the second work. In the �rst work, a 4-channel phased array based on a novel architecture incorporating a coupler and a noise-cancelling LNA in combination with a polyphase �lter was implemented to eliminate spatial co-channel blockers. This approach allows signal reception from all directions except from the direction of the blocker providing better than 20dB blocker cancellation in the X-band. The second work is aimed at achieving true simultaneous transmit-and-receive (STAR) performance through a hybrid coupler based full-duplex integrated N-path based circulator-Rx architecture. STAR radios enable higher spectrum e�ciency and dynamic spectrum access. Integrating the shared antenna-interface is attractive for small-form factor and MIMO channel estimation. Implemented for frequencies ranging from 550MHz to 900MHz this work addresses the challenge of low-noise wideband self-interference-cancellation by demonstrating a wide band hybrid-coupler circulator antenna interface using N-path mixers that achieves low noise �gure while preserving the linearity of passive-mixer �rst receiver. Better than +5.5dBm power handling of self-interference while providing over 40dB average cancellation over a bandwidth of 56MHz with a 2.7dB noise �gure has been measured. Further, the full-duplex circulator architecture has been expanded to a MIMO implementation wherein we demonstrate a 65nm CMOS 2.2GHz 2x2 FD MIMO RX that achieves up to 35/45dB average self-interference-cancellation (SIC) across 40/20MHz BW with more than 42dB/53dB average cross-talk (CT)-SIC across 40/20MHz BW. Interference cancellation mechanisms cause < 2.1dB degradation in RX NF and allows an overall TX power handling of +14dBm enabled by clock bootstrapping

On the feasibility and applications of in-band full-duplex radios for future wireless networks

Due to the continuous increase of the demands for the wireless network’s capacity, in-band full-duplex (IBFD) has recently become a key research topic due to its potential to double spectral efficiency, reduce latency, enhance emerging applications, etc., by transmitting and receiving simultaneously over the same channel. Meanwhile, many studies in the literature experimentally demonstrated the feasibility of IBFD radios, which leads to the belief that it is possible to introduce IBFD in the standard of the next-generation networks. Therefore, in this thesis, we timely study the feasibility of IBFD and investigate its advantages for emerging applications in future networks. In the first part, we investigate the interference suppression methods to maximize the IBFD gain by minimizing the effects of self-interference (SI) and co-channel interference (CCI). To this end, we first study a 3-step self-interference cancellation (SIC) scheme. We focus on the time domain-based analog canceller and nonlinear digital canceller, explaining their rationale, demonstrating their effectiveness, and finding the optimal design by minimizing the residual effects. To break the limitation of conventional electrical radio frequency (RF) cancellers, we study the photonic-assisted canceller (PAC) and propose a new design, namely a fiber array-based canceller. We propose a new low-complexity tuning algorithm for the PAC. The effectiveness of the proposed fiber array canceller is demonstrated via simulations. Furthermore, we construct a prototype of the fiber array canceller with two taps and carry out experiments in real-world environments. Results show that the 3-step cancellation scheme can bring the SI close to the receiver's noise floor. Then, we consider the multiple-input multiple-output (MIMO) scenarios, proposing to employ hybrid RF-digital beamforming to reduce the implementation cost and studying its effects on the SIC design. Additionally, we propose a user allocation algorithm to reduce the CCI from the physical layer. A heterogeneous industrial Internet of Things (IIoT) scenario is considered, while the proposed algorithm can be generalized by modifying the parameters to fit any other network. In the second part, we study the beamforming schemes for IBFD multi-cell multi-user (IBFD-MCMU) networks. The transceiver hardware impairments (HWIs) and channel uncertainty are considered for robustness. We first enhance zero-forcing (ZF) and maximum ratio transmission and combining (MRTC) beamforming to be compatible with IBFD-MCMU networks in the presence of multi-antenna users. Then, we study beamforming for SIC, which is challenging for MCMU networks due to the limited antennas but complex interference. We propose a minimum mean-squared error (MMSE)-based scheme to enhance the SIC performance while minimizing its effects on the sum rate. Furthermore, we investigate a robust joint power allocation and beamforming (JPABF) scheme, which approaches the performance of existing optimal designs with reduced complexity. Their performance is evaluated and compared through 3GPP-based simulations. In the third part, we investigate the advantages of applying IBFD radios for physical layer security (PLS). We focus on a channel frequency response (CFR)-based secret key generation (SKG) scheme in MIMO systems. We formulate the intrinsic imperfections of IBFD radios (e.g., SIC overheads and noise due to imperfect SIC) and derive their effects on the probing errors. Then we derive closed-form expressions for the secret key capacity (SKC) of the SKG scheme in the presence of a passive eavesdropper. We analyze the asymptotic behavior of the SKC in the high-SNR regime and reveal the fundamental limits for IBFD and half-duplex (HD) radios. Based on the asymptotic SKC, numerical results illustrate that effective analog self-interference cancellation (ASIC) is the basis for IBFD to gain benefits over HD. Additionally, we investigate essential processing for the CFR-based SKG scheme and verify its effectiveness via simulations and the National Institute of Standards and Technology (NIST) test. In the fourth part, we consider a typical application of IBFD radios: integrated sensing and communication (ISAC). To provide reliable services in high-mobility scenarios, we introduce orthogonal time frequency space (OTFS) modulation and develop a novel framework for OTFS-ISAC. We give the channel representation in different domains and reveal the limitations and disadvantages of existing ISAC frameworks for OTFS waveforms and propose a novel radar sensing method, including a conventional MUSIC algorithm for angle estimation and a delay-time domain-based range and velocity estimator. Additionally, we study the communication design based on the estimated radar sensing parameters. To enable reliable IBFD radios in high-mobility scenarios, a SIC scheme compatible with OTFS and rapidly-changing channels is proposed, which is lacking in the literature. Numerical results demonstrate that the proposed ISAC waveform and associated estimation algorithm can provide both reliable communications and accurate radar sensing with reduced latency, improved spectral efficiency, etc