816 research outputs found
Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band
Emerging health-monitor applications, such as information transmission
through multi-channel neural implants, image and video communication from
inside the body etc., calls for ultra-low active power (<50W) high
data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous
literature has strongly focused on low average power duty-cycled radios or low
power but low-date radios. In this paper, we investigate power performance
trade-off of each front-end component in a conventional radio including active
matching, down-conversion and RF/IF amplification and prioritize them based on
highest performance/energy metric. The analysis reveals 50 active
matching and RF gain is prohibitive for 50W power-budget. A mixer-first
architecture with an N-path mixer and a self-biased inverter based baseband
LNA, designed in TSMC 65nm technology show that sub 50W performance can
be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018
(VLSID
A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier
Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%
Radio hardware virtualization for software-defined wireless networks
Software-Defined Network (SDN) is a promising architecture for next generation Internet. SDN can achieve Network Function Virtualization much more efficiently than conventional architectures by splitting the data and control planes. Though SDN emerged first in wired network, its wireless counterpart Software-Defined Wireless Network (SDWN) also attracted an increasing amount of interest in the recent years. Wireless networks have some distinct characteristics compared to the wired networks due to the wireless channel dynamics. Therefore, network controllers present some extra degrees of freedom, such as taking measurements against interference and noise, or adapting channels according to the radio spectrum occupation. These specific characteristics bring about more challenges to wireless SDNs. Currently, SDWN implementations are mainly using customized firmware, such as OpenWRT, running on an embedded application processor in commercial WiFi chips, and restricted to layers above lower Media Access Control. This limitation comes from the fact that radio hardware usually require specific drivers, which have a proprietary implementation by various chipset vendors. Hence, it is difficult, if not impossible, to achieve virtualization on the radio hardware. However, this status has been changing as Software-Defined Radio (SDR) systems open up the entire radio communication stack to radio hobbyists and researchers. The bridge between SDR and SDN will make it possible to bring the softwarization and virtualization of wireless networks down to the physical layer, which will unlock the full potential of SDWN. This paper investigates the necessity and feasibility of extending the virtualization of wireless networks towards the radio hardware. A SDR architecture is presented for radio hardware virtualization in order to facilitate SDWN design and experimentation. We do believe that by adopting the virtualization-oriented hardware accelerator design presented here, an all-layer end-to-end high performance SDWN can be achieved
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Towards efficient and reconfigurable next-generation optical fronthaul networks for massive MIMO
This paper summaries our recent research on digital radio over fibre (DRoF) based optical fronthaul links and
experimentally demonstrates a novel last-mile wireless coverage system incorporating data compression, time-division
multiplexing (TDM) based packetization, and wavelength division multiplexing (WDM) based optical transmission.
Compression reduces the fronthaul data rate required per service by a factor of 3 when compared with the common public
radio interface (CPRI) standard, enabling efficient radio resource distribution over optical fibre infrastructure. The new
packetization mechanism and WDM architecture enable fully reconfigurable resource allocation in a fronthaul network for
20MHz-bandwidth RF inputs with 64x64 MIMO carried over an aggregated compressed optical data rate of 32Gbps using
4 wavelengths. The experimental results show over 40dB RF dynamic range with < 8% error value magnitude (EVM) for
the 64 quadrature amplitude modulation (64-QAM) input signals across all the WDM channels while the lowest EVM is
less than 2%. Meanwhile, this field-programmable gate array (FPGA) based DRoF system allows flexible, software
definable and easy-scalable dynamic antenna resource allocatio
On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration
Networks-on-Chip (NoCs) are emerging as the way
to interconnect the processing cores and the memory within
a chip multiprocessor. As recent years have seen a significant
increase in the number of cores per chip, it is crucial to guarantee
the scalability of NoCs in order to avoid communication to
become the next performance bottleneck in multicore processors.
Among other alternatives, the concept of Wireless Network-on-
Chip (WNoC) has been proposed, wherein on-chip antennas
would provide native broadcast capabilities leading to enhanced
network performance. Since energy consumption and chip area
are the two primary constraints, this work is aimed to explore
the area and energy implications of scaling a WNoC in terms of
(a) the number of cores within the chip, and (b) the capacity of
each link in the network. To this end, an integral design space
exploration is performed, covering implementation aspects (area
and energy), communication aspects (link capacity) and networklevel
considerations (number of cores and network architecture).
The study is entirely based upon analytical models, which will
allow to benchmark the WNoC scalability against a baseline
NoC. Eventually, this investigation will provide qualitative and
quantitative guidelines for the design of future transceivers for
wireless on-chip communication.Peer ReviewedPostprint (author’s final draft
Programmable photonics : an opportunity for an accessible large-volume PIC ecosystem
We look at the opportunities presented by the new concepts of generic programmable photonic integrated circuits (PIC) to deploy photonics on a larger scale. Programmable PICs consist of waveguide meshes of tunable couplers and phase shifters that can be reconfigured in software to define diverse functions and arbitrary connectivity between the input and output ports. Off-the-shelf programmable PICs can dramatically shorten the development time and deployment costs of new photonic products, as they bypass the design-fabrication cycle of a custom PIC. These chips, which actually consist of an entire technology stack of photonics, electronics packaging and software, can potentially be manufactured cheaper and in larger volumes than application-specific PICs. We look into the technology requirements of these generic programmable PICs and discuss the economy of scale. Finally, we make a qualitative analysis of the possible application spaces where generic programmable PICs can play an enabling role, especially to companies who do not have an in-depth background in PIC technology
Energy-Efficient Architecture for Receive Spatial Modulation in Large MIMO Systems
Cost and power consumption are substantial challenges
for multiple-input-multiple-output (MIMO) wireless communication
systems when the number of antennas and the
operating carrier frequency increase. We present a low cost
and low power consumption receive spatial modulation (RSM)
architecture based on a simple receiver design. We propose
a time-division-duplex (TDD) transmission protocol aimed to
reduce the training overhead where the channel knowledge is
required only at the base station. Simulation results presented
show that the power consumption and the energy efficiency
of the proposed RSM architecture outperform the hybrid and
conventional MIMO systems
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