Design, processing and testing of LSI arrays hybrid microelectronics task

Those factors affecting the cost of electronic subsystems utilizing LSI microcircuits were determined and the most efficient methods for low cost packaging of LSI devices as a function of density and reliability were developed

Development of an image converter of radical design

A long term investigation of thin film sensors, monolithic photo-field effect transistors, and epitaxially diffused phototransistors and photodiodes to meet requirements to produce acceptable all solid state, electronically scanned imaging system, led to the production of an advanced engineering model camera which employs a 200,000 element phototransistor array (organized in a matrix of 400 rows by 500 columns) to secure resolution comparable to commercial television. The full investigation is described for the period July 1962 through July 1972, and covers the following broad topics in detail: (1) sensor monoliths; (2) fabrication technology; (3) functional theory; (4) system methodology; and (5) deployment profile. A summary of the work and conclusions are given, along with extensive schematic diagrams of the final solid state imaging system product

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Ultrahigh areal number density solid-state on-chip microsupercapacitors via electrohydrodynamic jet printing

Microsupercapacitors (MSCs) have garnered considerable attention as a promising power source for microelectronics and miniaturized portable/wearable devices. However, their practical application has been hindered by the manufacturing complexity and dimensional limits. Here, we develop a new class of ultrahigh areal number density solid-state MSCs (UHD SS-MSCs) on a chip via electrohydrodynamic (EHD) jet printing. This is, to the best of our knowledge, the first study to exploit EHD jet printing in the MSCs. The activated carbon-based electrode inks are EHD jet-printed, creating interdigitated electrodes with fine feature sizes. Subsequently, a drying-free, ultraviolet-cured solid-state gel electrolyte is introduced to ensure electrochemical isolation between the SS-MSCs, enabling dense SS-MSC integration with on-demand (in-series/in-parallel) cell connection on a chip. The resulting on-chip UHD SS-MSCs exhibit exceptional areal number density [36 unit cells integrated on a chip (area = 8.0 mm x 8.2 mm), 54.9 cells cm(-2)] and areal operating voltage (65.9 V cm(-2))

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Development of effective thermal management strategies for LED luminaires

The efficacy, reliability and versatility of the light emitting diode (LED) can outcompete most established light source technologies. However, they are particularly sensitive to high temperatures, which compromises their efficacy and reliability, undermining some of the technology s key benefits. Consequently, effective thermal management is essential to exploit the technology to its full potential. Thermal management is a well-established subject but its application in the relatively new LED lighting industry, with its specific constraints, is currently poorly defined. The question this thesis aims to answer is how can LED thermal management be achieved most effectively? This thesis starts with a review of the current state of the art, relevant thermal management technologies and market trends. This establishes current and future thermal management constraints in a commercial context. Methods to test and evaluate the thermal management performance of a luminaire system follow. The defined test methods, simulation benchmarks and operational constraints provide the foundation to develop effective thermal management strategies. Finally this work explores how the findings can be implemented in the development and comparison of multiple thermal management designs. These are optimised to assess the potential performance enhancement available when applied to a typical commercial system. The outcomes of this research showed that thermal management of LEDs can be expected to remain a key requirement but there are hints it is becoming less critical. The impacts of some common operating environments were studied, but appeared to have no significant effect on the thermal behaviour of a typical system. There are some active thermal management devices that warrant further attention, but passive systems are inherently well suited to LED luminaires and are readily adopted so were selected as the focus of this research. Using the techniques discussed in this thesis the performance of a commercially available component was evaluated. By optimising its geometry, a 5 % decrease in absolute thermal resistance or a 20 % increase in average heat transfer coefficient and 10 % reduction in heatsink mass can potentially be achieved . While greater lifecycle energy consumption savings were offered by minimising heatsink thermal resistance the most effective design was considered to be one optimised for maximum average heat transfer coefficient. Some more radical concepts were also considered. While these demonstrate the feasibility of passively manipulating fluid flow they had a detrimental impact on performance. Further analysis would be needed to conclusively dismiss these concepts but this work indicates there is very little potential in pursuing them further

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk

Modelling and Design Optimisations of CMOS MEMS Single Membrane Thermopile Detector Arrays

Thermal imaging devices based on Complementary Metal-Oxide-Semiconductor (CMOS) and Micro-Electro-Mechanical System (MEMS) technology are widely used across consumer and industrial applications. The combination of CMOS and MEMS technologies allows for the production of devices with high performance, good reliability and consistent reproducibility. Additionally, these technologies allow devices to be manufactured at low cost and a high volume. There are several types of thermal sensing technologies, however, this thesis mainly focuses on 8×8 thermopile based Focal Plane Arrays (FPAs). The core principles governing the function of thermopiles are based on the Seebeck effect. In this thesis, the structure and fabrication process of thermopile FPAs are described and discussed. The thesis describes the functionality of the array chip and introduces a new experimental technique, called the bi-directional electrical biasing method, which was applied to obtain the device’s responsivity and crosstalk measurements. Compared to traditional measurement approaches using laser sources, this novel method significantly reduces the complexity of the experimental setup, as no external laser source is required. The crosstalk of the 8×8 array is ~2.69% and the responsivity is ~73.1 V/W. A detecting system using a larger array chip was designed, created and successfully applied in a series of experiments that involved gesture recognition and people counting. In order to enhance the performance of the current array device, a 3D simulation model based on the Finite Element Method (FEM) was built using the COMSOL Multiphysics simulation tool. The numerical model was validated by comparing the model’s simulated values for responsivity, crosstalk and temperature distribution with experimental results. The difference between the simulations and experimental results was 90 V/W in the model with tungsten tracks. A 32×32 array design demonstrates the smallest pixel size that can be achieved based on this thermopile array design. The 32×32 array design increased responsivity to ~77.18 V/W and crosstalk remained 6% when the pixel size was reduced further in a 64×64 array design, at this level of crosstalk, image quality is likely to be significantly affected. Future work may focus on the implementation of carbon nanotubes or novel 3D thermopile designs. Carbon nanotubes, when deposited over the array chip, could enhance the absorption of IR radiation. While new thermopiles employing a 3D design could dramatically reduce array size and potentially achieve a fill factor of 100%

Thermal performance enhancement of packaging substrates with integrated vapor chamber

The first part of this research investigates the effects of copper structures, such as copper through-package-vias (TPVs), and copper traces in redistribution layer (RDL), on the thermal performance of glass interposers through numerical and experimental approaches. Numerical parametric study on 2.5D interposers shows that as more copper structures are incorporated in glass interposers, the performance of silicon and glass interposers becomes closer, showing 31% difference in thermal resistance, compared to 53% difference without any copper structures in both interposers. In the second part of this study, a thermal model of glass interposer mounted on the vapor chamber integrated PCB is developed using multi-scale modeling scheme. The comparison of thermal performance between silicon and glass interposers shows that integration of vapor chamber with PCB makes thermal performance of both interposers almost identical, overcoming the limitation posed by low thermal conductivity of glass. The third part of this thesis focuses on design, fabrication, and performance measurement of PCB integrated with vapor chamber. Copper micropillar wick structure is fabricated on PCB with electroplating process, and its wettability is enhanced by silica nanoparticle coating. Design of the wick for the vapor chamber is determined based on the capillary performance and permeability test results. Fabricated device with ultra-thin thickness (~800 µm) shows higher thermal performance than copper plated PCB with the same thickness. Finally, 3D computational fluid dynamics/heat transfer model of the vapor chamber is developed, and modeling result is compared with test result.Ph.D