Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Development of a microfabricated silicon motor-driven compression system

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 2000.Includes bibliographical references (p. 237-243).by Luc G. Fréchette.Ph.D

Microlenses for optical microsystems

Tese de doutoramento (Programa Doutoral em Líderes para as Indústrias Tecnológicas)Lenses have been used by mankind for thousands of years for innumerous different reasons and applications. More recently, lenses in the micro scale dimension, so called microlenses (MLs), have been designed and fabricated using semiconductor technology. These new lenses are used for collimation, focusing or imaging and are an appealing alternative for applications where miniaturization and alignment simplicity are important requirements. Moreover, they also opened a large number of new applications for optical structures and, at the same time, reducing the mechanical and electrical complexity of the existing systems. In this context, the presented thesis has as main purposes, the design and development of a process that allows the fabrication of different sized plano-convex MLs with minor intervention on the process parameters. The MLs were fabricated using a photoresist, the AZ4562, through classical photolithography and the thermal reflow process. Another achievement was the fabrication of MLs directly on the surface of a silicon die containing complementary metal–oxide–semiconductor (CMOS) photodiodes (PDs) for quantifying the differences in their photocurrents generation capacity. The MLs’ optimum fabrication process was achieved when a 128k dots per inch (dpi) super high-resolution chrome on soda lime glass 3×3-0.060” photomask was employed. This photomask allows the design pattern to be transferred into the photoresist with very high precision. Nevertheless, for actually obtaining the desired lens profile, it is necessary to apply a thermal treatment to the fabricated microstructures. When the photoresist is submitted to a temperature higher than its glass transition temperature, it softens allowing the shape change to occur. For MLs, the major external force acting during this process is the surface tension. The fabricated MLs were structurally characterized using a profilometer and scanning electron microscope (SEM) images. For measuring the focal length, an optomechanical alignment system was assembled and a difference of just 4% was found between the measured and the theoretical values. An additional improvement was achieved by introducing a rehydration step in the fabrication process. The prebake stage used during the fabrication serves for evaporating the solvent off the photoresist but also, all of its water content. As a result, it was demonstrated that the AZ4562 needs rehydration in order to obtain excellent results by preventing structural damages in the MLs which are crucial for achieving efficient optical properties. The main advantage of this new optimized process is the further improvement of well-established standard microfabrication processes, i.e., photolithography combined with photoresist thermal reflow. Then, three approaches for integrating the MLs with the photodetecting substrate were tested. The first was using a polydimethylsiloxane (PDMS) intermediate layer for controlling the thickness between the MLs and the photodetecting substrate for allowing different focal lengths to be used depending on the application. The second one is setting the MLs’ focal length within the photodetectors’ depletion region using a 150 μm thin glass substrate for demonstrating that the current generation is enhanced for the same active area. Finally, the third approach consists on a setup composed by a MLs array fabricated directly on top of the PDs and in this approach, two solutions are presented. One is the fabrication of a ML on a square PD with the side measuring 24 μm. This setup enables the capture of light that would otherwise fall outside the photodiodes’ active area resulting in an overall photocurrent generation gain. The other is the fabrication of a MLs array using the same photomask but on a square PD with the side measuring 240 μm for determining the level of photocurrent generation. Moreover, two light sources (red and white lights) were used for evaluating the light acquisition enhancement capacity. From the results that were obtained under different integration solutions, the direct fabrication of MLs on PDs was the one with the better results concerning photocurrent generation by improving it by more than 14% and 2% for red and white lights, respectively. The red light has the ideal penetration depth in silicon for achieving the most prominent enhancement in photocurrent generation presented in this thesis. The MLs that were designed and fabricated, as well as their integration solutions with a photosensitive substrate, show interesting potential in applying them on industry standard fabrication processes for optical microsystems, from light-acquisition enhancement applications to image sensors.Desde há milhares de anos que a Humanidade tem usado lentes por inúmeras razões e para diferentes aplicações. Mais recentemente, têm sido desenvolvidas e fabricadas lentes de microdimensões, também designadas de microlentes (MLs), utilizando a tecnologia dos semicondutores. Este novo tipo de lentes é normalmente utilizado para colimar, focar ou criar imagens, e é uma alternativa apelativa para aplicações onde a miniaturização e simplicidade de alinhamento são requisitos importantes. Além disso, elas também deram origem a um conjunto de novas aplicações para estruturas óticas reduzindo, ao mesmo tempo, as complexidades mecânicas e elétricas dos sistemas existentes. Nesta perspetiva, a presente tese tem como principais objetivos o desenho e desenvolvimento de um processo que permita o fabrico de MLs plano-convexas de diferentes tamanhos com intervenção mínima nos parâmetros do processo. As MLs foram fabricadas utilizando um polímero fotosensível (PF), o AZ4562, através de fotolitografia e refluxo térmico. Outro objetivo foi o fabrico de MLs diretamente na superfície de um die de silício, que contém fotodíodos (FDs) em tecnologia complementary metal–oxide semiconductor (CMOS), para quantificar as diferenças na sua capacidade de gerar fotocorrente (FC). O processo de fabrico ótimo de MLs foi alcançado quando uma fotomáscara (FM) de crómio de super alta-resolução de 128k dots per inch (dpi) foi usada. Esta FM permite que o desenho-padrão seja transferido para o PF com elevada precisão. No entanto, para se obter o perfil de lente, é necessário aplicar um tratamento térmico à microestrutura fabricada. Quando o PF é submetido a uma temperatura mais alta do que a sua temperatura de transição vítrea, este amolece permitindo assim que a sua forma se altere. No caso das MLs, a principal força responsável para que essa mudança ocorra durante este processo térmico é a tensão superficial. As MLs fabricadas, foram estruturalmente caracterizadas usando um perfilómetro e imagens de scanning electron microscope (SEM). Para medir a distância focal (f), foi concebido um sistema de alinhamento opto-mecânico e verificou-se que existe uma pequena diferença de 4% entre o valor medido e o calculado. Foi conseguida ainda uma melhoria adicional com a introdução de uma fase de reidratação no processo de fabrico. A fase de prebake utilizada no fabrico serve para evaporar os solventes do PF mas, todavia, retira também todo o seu conteúdo de água. Por isso, foi demonstrado que o AZ4562 necessita de ser reidratado para se conseguir excelentes resultados prevenindo danos estruturais nas MLs que é fundamental para a obtenção de propriedades óticas eficientes. A maior vantagem neste novo processo otimizado é a melhoria conseguida nos processos de microfabricação standard estabelecidos, i.e., fotolitografia combinada com o refluxo térmico do PF. Em seguida, foram testadas três formas para integrar as MLs num substrato fotossensível. A primeira consistiu em utilizar uma camada intermédia de polidimetilssiloxano (PDMS) para controlar a espessura entre as MLs e o substrato fotodetetor e assim, permitir a utilização de diferentes f dependendo da aplicação. A segunda foi colocar f dentro da região de depleção do FD usando um substrato de vidro com 150 μm de espessura demonstrando que a geração de FC é aumentada para a área ativa. Por último, a terceira abordagem foi o desenvolvimento de um setup composto por um array de MLs fabricado diretamente sobre os FDs e duas soluções são apresentadas. Uma delas é o fabrico de uma ML num FD quadrado com 24 μm de lado. Este setup permite a captura de luz que não iria incidir na área ativa do FD resultando num aumento de geração de FC. O outro é o fabrico de um array de MLs usando a mesma FM, mas num FD quadrado com 240 μm de lado, para determinar o nível de geração de FC. Nestes testes, recorreu-se a duas fontes de luz (vermelha e branca) para avaliar a capacidade de aumentar a aquisição de luz. Relativamente à geração de FC, o melhor dos resultados obtidos nas várias soluções de integração propostas, foi conseguido com o fabrico direto de MLs nos FDs com aumentos superiores a 14% e 2% para as luzes vermelha e branca, respetivamente. A luz vermelha tem a penetração ideal no silício para atingir os resultados mais proeminentes no que concerne aos ganhos obtidos na geração de FC apresentado nesta tese. As MLs que foram desenhadas e fabricadas, bem como as soluções propostas de integração num substrato fotossensível, demonstram um potencial interesse de aplicação em processos industriais de fabrico standard para microsistemas óticos, desde aplicações de aumento de aquisição de luz, até sensores de imagens

Ultra-thin silicon technology for tactile sensors

In order to meet the requirements of high performance flexible electronics in fast growing portable consumer electronics, robotics and new fields such as Internet of Things (IoT), new techniques such as electronics based on nanostructures, molecular electronics and quantum electronics have emerged recently. The importance given to the silicon chips with thickness below 50 μm is particularly interesting as this will advance the 3D IC technology as well as open new directions for high-performance flexible electronics. This doctoral thesis focusses on the development of silicon–based ultra-thin chip (UTC) for the next generation flexible electronics. UTCs, on one hand can provide processing speed at par with state-of-the-art CMOS technology, and on the other provide the mechanical flexibility to allow smooth integration on flexible substrates. These development form the motivation behind the work presented in this thesis. As the thickness of any silicon piece decreases, the flexural rigidity decreases. The flexural rigidity is defined as the force couple required to bend a non-rigid structure to a unit curvature, and therefore the flexibility increases. The new approach presented in this thesis for achieving thin silicon exploits existing and well-established silicon infrastructure, process, and design modules. The thin chips of thicknesses ranging between 15 μm – 30 μm, were obtained from processed bulk wafer using anisotropic chemical etching. The thesis also presents thin wafer transfer using two-step transfer printing approach, packaging by lamination or encapsulation between two flexible layerand methods to get the electrical connections out of the chip. The devices realised on the wafer as part of front-end processing, consisted capacitors and transistors, have been tested to analyse the effect of bending on the electrical characteristics. The capacitance of metal-oxide-semiconductor (MOS) capacitors increases by ~5% during bending and similar shift is observed in flatband and threshold voltages. Similarly, the carrier mobility in the channel region of metal-oxide-semiconductor field effect transistor (MOSFET) increases by 9% in tensile bending and decreases by ~5% in compressive bending. The analytical model developed to capture the effect of banding on device performance showed close matching with the experimental results. In order to employ these devices as tactile sensors, two types of piezoelectric materials are investigated, and used in extended gate configuration with the MOSFET. Firstly, a nanocomposite of Poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE) and barium titanate (BT) was developed. The composite, due to opposite piezo and pyroelectric coefficients of constituents, was able to suppress the sensitivity towards temperature when force and temperature varied together, The sensitivity to force in extended gate configuration was measured to be 630 mV/N, and sensitivity to temperature was 6.57 mV/oC, when it was varied during force application. The process optimisation for sputtering piezoelectric Aluminium Nitride (AlN) was also carried out with many parametric variation. AlN does not require poling to exhibit piezoelectricity and therefore offers an attractive alternative for the piezoelectric layer used in devices such as POSFET (where piezoelectric material is directly deposited over the gate area of MOSFET). The optimised process gave highly orientated columnar structure AlN with piezoelectric coefficient of 5.9 pC/N and when connected in extended gate configuration, a sensitivity (normalised change in drain current per unit force) of 2.65 N-1 was obtained

Fabrication and analysis of 4H-SiC diodes

Despite the excellent electrical and thermal properties of 4H-silicon carbide (SiC) and the advancements in the field of 4H-SiC epitaxial growth, the existence of defects in the material can considerably reduce the electrical performance of the SiC power devices. Defects can result in low carrier lifetime affecting the on-state resistance of bipolar devices, such as PiN diodes, and increased leakage current affecting the reverse blocking performance of power devices, such as Schottky diodes. A commonly found surface morphological defect in available 4H-SiC substrates is the triangular defect. In this thesis, the formation mechanism of this defect and its impact on the electrical performance of the fabricated 4H-SiC PiN diodes is discussed. 4H-SiC PiN diodes were intentionally fabricated on the triangular defects and in areas with no visible morphological defects. The devices were then packaged and tested to assess the impact of these defects on the resulting on-state and reverse leakage characteristics. It was shown for the first time the impact of triangular defects on switching characteristics of 4H-SiC PiN diodes fabricated on- and off-defects. Moreover, triangular defects were characterised using methods including AFM, SEM, Photoluminescence and HRTEM. Other complex structures were observed on the triangular defect using HRTEM such as double positioning boundary (DPB), which resulted in a leakage path through the drift region of the devices and increased the leakage current. Furthermore, this thesis focuses on the fabrication and analysis of 4H-SiC power diodes for high voltage applications with particular focus on improving the performance of 4H-SiC SBDs using a novel metal-semiconductor interface treatment and 4H-SiC PiN diodes using high temperature processing techniques to improve the carrier lifetime, on-state resistance and conductivity modulation of the diode. Carrier lifetime enhancement in 4H-SiC PiN diodes in this thesis was achieved using a combined high temperature oxidation and successive argon annealing process at 1550°C for 1 hour. This resulted in an increase of nearly 45% of the reverse recovery current and approximately 40% of the carrier lifetime. The findings of this study could be potentially used for other 4H-SiC bipolar devices such as IGBTs, BJTs and thyristors. This thesis has also investigated the impact of various surface passivation treatments to improve the quality of the 4H-SiC surface and the metal-semiconductor interface using Mo/Ti, and Ni-4H-SiC Schottky diodes. The most significant outcome of this investigation was the performance of P2O5 treated Mo/SiC Schottky diodes which retained a barrier height equivalent to that of titanium, but with a leakage current lower than any Ni diode, seemingly combining the benefits of both a low- and high-SBH metal. Furthermore, P2O5 treated Mo/SiC Schottky diodes were the only diodes to undergo any significant leakage current reduction after any of the pre-treatments exhibiting exceptionally low leakage, even at 300°C. XPS and SIMS analysis on all Mo/SiC SBDs revealed that the stoichiometry of the SiC underneath the contact was enhanced using P2O5 treatment and that traces of P2O5 were found after removal of the passivation layer and post-treatment metallisation. It was also found that the Mo-4HSiC interface on the P2O5 treated sample was very sharp and uniform compared to the untreated sample where Mo-SiC interface looks uneven and cloudy. The developed novel metal-semiconductor interface treatment can be potentially used for MOS interface improvements

The communicative theory of Terminology (CTT) applied to the development of a corpus-based specialised dictionary of the ceramics industry

Esta tesis es el resultado de un proyecto destinado a la creación de un diccionario activo, bilingüe (español-inglés; inglés-español) y especializado de la industria cerámica y azulejera con la Teoría Comunicativa de la Terminología como su pilar teórico principal. Debido al posicionamiento teórico adoptado, la investigación aquí presentada ha partido de un estudio de corpus (compilado ad hoc) en el que los términos han sido analizados in vivo y caracterizados de acuerdo al ¿habitat¿ en el que se hallan en el texto especializado. Así pues, la aproximación hecha al estudio de la terminología industrial cerámica hace pertinente el uso de la etiqueta ¿lexicografía especializada¿ a la hora de referirnos a un trabajo como éste en el que se ha tratado de ir más allá de la práctica terminográfica para dar lugar a un estudio en el que se prima el contexto, las asociaciones naturales de los términos (colocaciones) y la naturaleza comunicativa de la terminología. De este modo, en esta tesis se ha presentado de manera progresiva, además de un marco teórico detallado y coherente con el fin último de la investigación, la metodología utilizada para la elaboración del diccionario en curso, ampliamente basada en el uso de programas informáticos tanto para la explotación del corpus (WordSmith Tools 4.0), como para la creación de la base de datos terminológica (TermStar XV) y la generación de entradas finales (GENDIC).Así pues, esta tesis presenta de manera progresiva los resultados obtenidos en cada etapa del método de trabajo y 4,000 entradas finales (en este caso del inglés al español) correspondientes a las letras A, B, N, O, U y V del diccionario.This PhD dissertation is the result of an ongoing process aimed at the creation of a bilingual corpus-based specialised active dictionary of the ceramic industry, with the Communicative Theory of Terminology (CTT) as its mainstay. According to the grounding principles of the CTT, this research has departed form a corpus-based approach in which terms have been analysed in vivo and characterised from the natural habitat in which they are given in specialised communication/discourse. In this light, it has been put forward how the study of terms – made possible thanks to the activity of compiling and describing them, called terminography – may be complemented by the wider projection of specialised lexicography for the compilation and elaboration of LSP, user-oriented and user-friendly quality products in the form of dictionaries. This specialised lexicographical dimension of the work has necessarily implied the need to renew the concept of speciality language dictionaries applied to the ceramic industry and has given way to the creation of a (prospective) active dictionary in this field with a marked emphasis on context. Accordingly, the importance of pragmatic aspects in a work of this sort, has made it necessary to undertake an in-depth revision and analysis of the socio-economic context for the research in order be able to establish and solve the specific terminological needs that the ceramic industrial discourse community may find. On the basis of this theoretical framework, the method of study followed for the development of the prospective dictionary has comprised 8 broad stages: the stage of work preparation and corpus compilation, the elaboration of the field diagram, the stage of documentary corpus management, term extraction, data processing, revision and normalisation and finally, the edition stage. Two main types of results have been presented: those obtained through work in progress in the different stages of the method and final ones strictly speaking, that is, 4,000 English-Spanish entries in their final format (as they will appear in the prospective dictionary) belonging to the letters A, B, N, O, U and V of a complete dictionary which will include a total of 26,000 entries

EUROSENSORS XVII : book of abstracts

Fundação Calouste Gulbenkien (FCG).Fundação para a Ciência e a Tecnologia (FCT)