Evolutionary algorithm for state encoding

This paper presents an encoding technique that is common for many different logic synthesis problems. It enables us to construct a system of Boolean functions, and then to decompose this system into sub-systems in such a way that a dependency of functions, included into each sub-system, on the respective arguments is reduced. For complex applications such type of encoding has a high computational complexity and the paper proposes a novel evolutionary algorithm for the solution of this problemIFIP International Conference on Artificial Intelligence in Theory and Practice - Evolutionary ComputationRed de Universidades con Carreras en Informática (RedUNCI

Evolutionary algorithm for state encoding

This paper presents an encoding technique that is common for many different logic synthesis problems. It enables us to construct a system of Boolean functions, and then to decompose this system into sub-systems in such a way that a dependency of functions, included into each sub-system, on the respective arguments is reduced. For complex applications such type of encoding has a high computational complexity and the paper proposes a novel evolutionary algorithm for the solution of this problemIFIP International Conference on Artificial Intelligence in Theory and Practice - Evolutionary ComputationRed de Universidades con Carreras en Informática (RedUNCI

A genetic parallel programming based logic circuit synthesizer.

Lau, Wai Shing.Thesis submitted in: November 2006.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (leaves 85-94).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Field Programmable Gate Arrays --- p.2Chapter 1.2 --- FPGA technology mapping problem --- p.3Chapter 1.3 --- Motivations --- p.5Chapter 1.4 --- Contributions --- p.6Chapter 1.5 --- Thesis Organization --- p.9Chapter 2 --- Background Study --- p.11Chapter 2.1 --- Deterministic approach to technology mapping problem --- p.11Chapter 2.1.1 --- FlowMap --- p.12Chapter 2.1.2 --- DAOMap --- p.14Chapter 2.2 --- Stochastic approach --- p.15Chapter 2.2.1 --- Bio-Inspired Methods for Multi-Level Combinational Logic Circuit Design --- p.15Chapter 2.2.2 --- A Survey of Combinational Logic Circuit Representations in stochastic algorithms --- p.17Chapter 2.3 --- Genetic Parallel Programming --- p.20Chapter 2.3.1 --- Accelerating Phenomenon --- p.22Chapter 2.4 --- Chapter Summary --- p.23Chapter 3 --- A GPP based Logic Circuit Synthesizer --- p.24Chapter 3.1 --- Overall system architecture --- p.25Chapter 3.2 --- Multi-Logic-Unit Processor --- p.26Chapter 3.3 --- The Genotype of a MLP program --- p.28Chapter 3.4 --- The Phenotype of a MLP program --- p.31Chapter 3.5 --- The Evolution Engine --- p.33Chapter 3.5.1 --- The Dual-Phase Approach --- p.33Chapter 3.5.2 --- Genetic operators --- p.35Chapter 3.6 --- Chapter Summary --- p.38Chapter 4 --- MLP in hardware --- p.39Chapter 4.1 --- Motivation --- p.39Chapter 4.2 --- Hardware Design and Implementation --- p.40Chapter 4.3 --- Experimental Settings --- p.43Chapter 4.4 --- Experimental Results and Evaluations --- p.46Chapter 4.5 --- Chapter Summary --- p.50Chapter 5 --- Feasibility Study of Multi MLPs --- p.51Chapter 5.1 --- Motivation --- p.52Chapter 5.2 --- Overall Architecture --- p.53Chapter 5.3 --- Experimental settings --- p.55Chapter 5.4 --- Experimental results and evaluations --- p.59Chapter 5.5 --- Chapter Summary --- p.59Chapter 6 --- A Hybridized GPPLCS --- p.61Chapter 6.1 --- Motivation --- p.62Chapter 6.2 --- Overall system architecture --- p.62Chapter 6.3 --- Experimental settings --- p.64Chapter 6.4 --- Experimental results and evaluations --- p.66Chapter 6.5 --- Chapter Summary --- p.70Chapter 7 --- A Memetic GPPLCS --- p.71Chapter 7.1 --- Motivation --- p.72Chapter 7.2 --- Overall system architecture --- p.72Chapter 7.3 --- Experimental settings --- p.76Chapter 7.4 --- Experimental results and evaluations --- p.77Chapter 7.5 --- Chapter Summary --- p.80Chapter 8 --- Conclusion --- p.82Chapter 8.1 --- Future work --- p.83Bibliography --- p.8

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits

Considerable progress has been made recently 1n the understanding of combinational logic optimization. Consequently a large number of university and industrial Electric Computing Aided Design (ECAD) programs are now available for optimal logic synthesis of combinational circuits. The progress with sequential logic synthesis and optimization, on the other hand, is considerably less mature. In recent years, evolutionary algorithms have been found to be remarkably effective way of using computers for solving difficult problems. This thesis is, in large part, a concentrated effort to apply this philosophy to the synthesis and optimization of sequential circuits. A state assignment based on the use of a Genetic Algorithm (GA) for the optimal synthesis of sequential circuits is presented. The state assignment determines the structure of the sequential circuit realizing the state machine and therefore its area and performances. The synthesis based on the GA approach produced designs with the smallest area to date. Test results on standard fmite state machine (FS:M) benchmarks show that the GA could generate state assignments, which required on average 15.44% fewer gates and 13.47% fewer literals compared with alternative techniques. Hardware evolution is performed through a succeSSlOn of changes/reconfigurations of elementary components, inter-connectivity and selection of the fittest configurations until the target functionality is reached. The thesis presents new approaches, which combine both genetic algorithm for state assignment and extrinsic Evolvable Hardware (EHW) to design sequential logic circuits. The implemented evolutionary algorithms are able to design logic circuits with size and complexity, which have not been demonstrated in published work. There are still plenty of opportunities to develop this new line of research for the synthesis, optimization and test of novel digital, analogue and mixed circuits. This should lead to a new generation of Electronic Design Automation tools.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Dynamically reconfigurable bio-inspired hardware

During the last several years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bitstream, providing high architectural flexibility, while guaranteeing high performance. These configurability features have received special interest from computer architects: one can find several reconfigurable coprocessor architectures for cryptographic algorithms, image processing, automotive applications, and different general purpose functions. On the other hand we have bio-inspired hardware, a large research field taking inspiration from living beings in order to design hardware systems, which includes diverse topics: evolvable hardware, neural hardware, cellular automata, and fuzzy hardware, among others. Living beings are well known for their high adaptability to environmental changes, featuring very flexible adaptations at several levels. Bio-inspired hardware systems require such flexibility to be provided by the hardware platform on which the system is implemented. In general, bio-inspired hardware has been implemented on both custom and commercial hardware platforms. These custom platforms are specifically designed for supporting bio-inspired hardware systems, typically featuring special cellular architectures and enhanced reconfigurability capabilities; an example is their partial and dynamic reconfigurability. These aspects are very well appreciated for providing the performance and the high architectural flexibility required by bio-inspired systems. However, the availability and the very high costs of such custom devices make them only accessible to a very few research groups. Even though some commercial FPGAs provide enhanced reconfigurability features such as partial and dynamic reconfiguration, their utilization is still in its early stages and they are not well supported by FPGA vendors, thus making their use difficult to include in existing bio-inspired systems. In this thesis, I present a set of architectures, techniques, and methodologies for benefiting from the configurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems. Among the presented architectures there are neural networks, spiking neuron models, fuzzy systems, cellular automata and random boolean networks. For these architectures, I propose several adaptation techniques for parametric and topological adaptation, such as hebbian learning, evolutionary and co-evolutionary algorithms, and particle swarm optimization. Finally, as case study I consider the implementation of bio-inspired hardware systems in two platforms: YaMoR (Yet another Modular Robot) and ROPES (Reconfigurable Object for Pervasive Systems); the development of both platforms having been co-supervised in the framework of this thesis

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits.

Considerable progress has been made recently 1n the understanding ofcombinational logic optimization. Consequently a large number of universityand industrial Electric Computing Aided Design (ECAD) programs are nowavailable for optimal logic synthesis of combinational circuits. The progresswith sequential logic synthesis and optimization, on the other hand, isconsiderably less mature.In recent years, evolutionary algorithms have been found to be remarkablyeffective way of using computers for solving difficult problems. This thesis is,in large part, a concentrated effort to apply this philosophy to the synthesisand optimization of sequential circuits.A state assignment based on the use of a Genetic Algorithm (GA) for theoptimal synthesis of sequential circuits is presented. The state assignmentdetermines the structure of the sequential circuit realizing the state machineand therefore its area and performances. The synthesis based on the GAapproach produced designs with the smallest area to date. Test results onstandard fmite state machine (FS:M) benchmarks show that the GA couldgenerate state assignments, which required on average 15.44% fewer gatesand 13.47% fewer literals compared with alternative techniques.Hardware evolution is performed through a succeSSlOn ofchanges/reconfigurations of elementary components, inter-connectivity andselection of the fittest configurations until the target functionality is reached.The thesis presents new approaches, which combine both genetic algorithmfor state assignment and extrinsic Evolvable Hardware (EHW) to designsequential logic circuits. The implemented evolutionary algorithms are able todesign logic circuits with size and complexity, which have not beendemonstrated in published work.There are still plenty of opportunities to develop this new line of research forthe synthesis, optimization and test of novel digital, analogue and mixedcircuits. This should lead to a new generation of Electronic DesignAutomation tools