Design tool and methodologies for interconnect reliability analysis in integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 195-204).by Syed Mohiul Alam.Ph.D

New methodologies for interconnect reliability assessments of integrated circuits

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2000.Includes bibliographical references (leaves 245-251).The stringent performance and reliability demands that will accompany the development of next-generation circuits and new metallization technologies will require new and more accurate means of assessing interconnect reliability. Reliability assessments based on conventional methodologies are flawed in a number of very important ways, including the disregard of the effects of complex interconnect geometries on reliability. New models, simulations and experimental methodologies are required for the development of tools for circuit-level and process-sensitive reliability assessments. Most modeling and experimental characterization of interconnect reliability has focused on simple straight lines terminating at pads or vias. However, laid-out integrated circuits usually have many interconnects with junctions and wide-to-narrow transitions. In carrying out circuit-level reliability assessments it is important to be able to assess the reliability of these more complex shapes, generally referred to as "trees". An interconnect tree consists of continuously connected high-conductivity metal within one layer of metallization. Trees terminate at diffusion barriers at vias and contacts, and, in the general case, can have more than one terminating branch when the tree includes junctions. We have extended the understanding of "immortality" demonstrated and analyzed for straight stud-to-stud lines, to trees of arbitrary complexity. We verified the concept of immortality in interconnect trees through experiments on simple tree structures. This leads to a hierarchical approach for identifying immortal trees for specific circuit layouts and models for operation. We suggest a computationally efficient and flexible strategy for assessment of the reliability of entire integrated circuits. The proposed hierarchical reliability analysis can provide reliability assessments during the design and layout process (Reliability Computer Aided Design, RCAD). Design rules are suggested based on calculations of the electromigration-induced development of inhomogeneous steadystate mechanical stress states. Failure of interconnects by void nucleation in single-layermetallization, as well as failure by void growth in the presence of refractory metal shunt layers are taken into account. The proposed methodology identifies a large fraction of interconnect trees in a typical design as immune to electromigration-induced failure. To complete a circuit-level-reliability analysis, it is also necessary to estimate the lifetimes of the mortal trees. We have developed simulation tools that allow modeling of stress evolution and failure in arbitrarily complex trees. We have demonstrated the validity of these models and simulations through comparisons with experiments on simple trees, such as "L"- and "T"-shaped trees with different current configurations. Because analyses made using simulations are computationally intensive, simulations should be used for analysis of the least reliable trees. The reliability of the majority of the mortal trees can be assessed using a conservative default model based on nodal reliability analyses for the assessment of electromigration-limited reliability of interconnect trees. The lifetimes of the nodes are calculated by estimating the times for void nucleation, void growth to failure, and formation of extrusions. The differences between straight stud-to-stud lines and interconnect trees are studied by investigating the effects of passive and active reservoirs on electromigration. Models and simulations were validated through comparisons with experiments on simple tree structures, such as lines broken into two limbs with different currents in each limb. Models, simulations and experimental results on the reliability of interconnect trees are shown to yield mutually consistent results. Taken together, the results from this research have provided the basis for the development of the first RCAD tool capable of accurate circuit-level, processing sensitive and layout-specific reliability analyses.by Stefan P. Hau-Riege.Ph.D

An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

A Manufacturer Design Kit for Multi-Chip Power Module Layout Synthesis

The development of Multi-Chip Power Modules (MCPMs) has been a key factor in recent advancements in power electronics technologies. MCPMs achieve higher power density by combining multiple power semiconductor devices into one package. The work detailed in this thesis is part of an ongoing project to develop a computer-aided design software tool known as PowerSynth for MCPM layout synthesis and optimization. This thesis focuses on the definition and design of a Manufacturer Design Kit (MDK) for PowerSynth, which enables the designer to design an MCPM for a manufacturer’s fabrication process. The MDK is comprised of a layer stack and technology library, design rule checking (DRC), and layout versus schematic checking. File formats have been defined for layer stack and design rule input, and import functions have been written and integrated with the existing user interface and data structures to allow PowerSynth to accept these file formats as a form of input. Finally, an exhaustive DRC function has been implemented to allow the designer to verify that a synthesized layout meets all design rules before committing the design to manufacturing. This function was validated by running DRC on an example layout solution using two different sets of design rules

An Approach to Assess Solder Interconnect Degradation Using Digital Signal

Department of Human and Systems EngineeringDigital signals used in electronic systems require reliable data communication. It is necessary to monitor the system health continuously to prevent system failure in advance. Solder joints in electronic assemblies are one of the major failure sites under thermal, mechanical and chemical stress conditions during their operation. Solder joint degradation usually starts from the surface where high speed signals are concentrated due to the phenomenon referred to as the skin effect. Due to the skin effect, high speed signals are sensitive when detecting the early stages of solder joint degradation. The objective of the thesis is to assess solder joint degradation in a non-destructive way based on digital signal characterization. For accelerated life testing the stress conditions were designed in order to generate gradual degradation of solder joints. The signal generated by a digital signal transceiver was travelling through the solder joints to continuously monitor the signal integrity under the stress conditions. The signal properities were obtained by eye parameters and jitter, which represented the characteristics of the digital signal in terms of noise and timing error. The eye parameters and jitter exhibited significant increase after the exposure of the solder joints to the stress conditions. The test results indicated the deterioration of the signal integrity resulted from the solder joint degradation, and proved that high speed digital signals could serve as a non-destructive tool for sensing physical degradation. Since this approach is based on the digital signals used in electronic systems, it can be implemented without requiring additional sensing devices. Furthermore, this approach can serve as a proactive prognostic tool, which provides real-time health monitoring of electronic systems and triggers early warning for impending failure.ope

A thermal simulation process based on electrical modeling for complex interconnect, packaging, and 3DI structures

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost. © 2006 IEEE.published_or_final_versio

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175

System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude