Design optimization for low light CMOS image sensors readout chain

Email Print Request Permissions For a CIS readout chain based on 4T pixel, column amplification and CDS, we confirm that thermal noise can be reduced to be neglected compared to 1/f noise using parameters independent of the pixel design, namely column level gain, bandwidth control or correlated multiple sampling (CMS). Based on analytic noise calculation and simulation results using 180nm process, we show that CMS has no advantage over CDS for thermal noise reduction but offers slightly more 1/f noise reduction (about 20% less 1/f noise if high number of samples is used). 1/f and RTS noise originating from the in-pixel source follower transistor are reported to be the dominant noise sources in CIS readout chain. Based on analytic noise calculation, we demonstrate that, for a given CMOS process, the input referred 1/f noise is minimal for a unique pair of gate dimensions of the in-pixel source follower and we give its expression as a function of technological parameters

A 0.4 e-rms Temporal Readout Noise 7.5 µm Pitch and a 66% Fill Factor Pixel for Low Light CMOS Image Sensors

This paper explores a new way to reduce the readout noise for CMOS image sensors by using a typical 4T pixel embedding a PMOS source follower with reduced oxide thickness and gate dimensions. This approach is confirmed by a test chip designed in a 180 nm CIS CMOS process, and embedding small arrays of the proposed new pixels together with state-of-the-art 4T pixels for comparison. The new pixels feature a pitch of 7.5 µm and a fill factor of 66%. A 0.4 erms input-referred noise and a 185 µV/e- conversion gain are obtained. Compared to stateof-the-art pixels, also present onto the test chip, the RMS noise is divided by more than 2 and the conversion gain is multiplied by 2.2

A correlated multiple sampling passive switched capacitor circuit for low light CMOS image sensors

After a brief review of the principle of correlated multiple sampling (CMS) and its implementation techniques in CIS readout chains, a simple CMS passive circuit that (i) requires no additional active circuitry, (ii) has no impact on the output dynamic range and (iii) does not need multiple analog-to-digital conversions (faster) is presented. The proposed circuit uses n switched capacitors to perform a CMS on 2n samples. It is validated using transient noise simulations on a CIS readout chain based on a 4T pixel, designed with a 180nm CIS process. For a line readout time of 35 μs and a column amplifier bandwidth of 256 kHz, the proposed circuit reduces the input-referred noise as expected by an ideal CMS

A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process

A sub-0.5e−rms temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18μm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5μm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5μA the sensor chip features an input-referred noise histogram from 0.25 e−rms to a few e−rms peaking at 0.48 e−rms. The imager features a full well capacity of 6400 e− and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6e-/s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3 e(rms)(-) read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used

DESIGN OF A BURST MODE ULTRA HIGH-SPEED LOW-NOISE CMOS IMAGE SENSOR

Ultra-high-speed (UHS) image sensors are of interest for studying fast scientific phenomena and may also be useful in medicine. Several published studies have recently achieved frame rates of up to millions of frames per second (Mfps) using advanced processes and/or customized processes. This thesis presents a burst-mode (108 frames) UHS low-noise CMOS image sensor (CIS) based on charge-sweep transfer gates in an unmodified, standard 180 nm front-side-illuminated CIS process. By optimizing the photodiode geometry, the 52.8 μm pitch pixels with 20x20 μm^2 of active area, achieve a charge-transfer time of less than 10 ns. A proof-of-concept CIS was designed and fabricated. Through characterization, it is shown that the designed CIS has the potential to achieve 20 Mfps with an input-referred noise of 5.1 e− rms

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Ultra Low Noise CMOS Image Sensors

CMOS Image Sensors (CIS) overtook the charge coupled devices (CCDs) in low noise performance. Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. This work presents a review of CMOS image sensors based on pinned photo diodes (PPDs). The latter includes the historical background, the PPD physics and the readout chain circuits used for low-noise performance. The physical mechanisms behind the random fluctuations affecting the signal at different levels of conventional CIS readout chains are reviewed and clarified. This thesis dedicates a particular focus to the readout circuit noise given that it precludes photoelectron counting in conventional CIS. A detailed analytical calculation of the temporal read noise (TRN) in conventional CIS readout chain is presented. The latter suggests different noise reduction techniques at process and circuit design level. Among the noise reduction techniques suggested by the analytical noise calculation, the increase of the oxide capacitance by using a thin oxide in-pixel amplifying transistor, for low 1/f noise, is suggested for the first time. A test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 e-rms has been measured. Compared with the state-of-the-art pixels, also present onto the test chip, the mean RMS noise is divided by more than 2. Based on these encouraging result, a full VGA (640H×480V) imager has been integrated in a standard CIS process. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. The sensor chip features an input-referred noise histogram from 0.25 e-rms to a few e-rms peaking at 0.48 e-rms. This sub-0.5 electron noise performance is obtained with a full well capacity of 6400 e- and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e-/s. Correlated multiple sampling (CMS) is a noise reduction technique commonly used in low noise CIS. This work presents an original design for CMS based on a passive switched-capacitor network, with a minimum number of capacitors. The proposed circuit requires no additional active circuitry, has no impact on the output dynamic range and does not need multiple analog-to-digital conversions. It was verified with transient noise simulations and shows a noise reduction in perfect agreement with ideal CMS. For a future perspective, the impact of the technology downscale on CIS sensitivity from an electronic read noise aspect is investigated. Active imaging in the Terahertz (THz) band is an emerging technology. Source modulation combined with a selective filtering can be used to reduce the noise in CMOS THz imagers. This work presents the first integration of a 1 kpixel CMOS THz imager integrating, in each pixel, a metal antenna with a MOS rectifier, low noise amplification and highly selective filtering, based on a switch-capacitor N-path filter combined with a broad band Gm-C filter. The latter has been tested successfully. An input-referred noise of 0.2 µV RMS corresponding to a total noise equivalent THz power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz