Low Power Reversible Parallel Binary Adder/Subtractor

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa

Optimized Reversible Logic Multiplexer Designs for Energy-Efficient Nanoscale Computing

Nano- and quantum-based low-power applications are where reversible logic really shines. By using digitally equivalent circuits with reversible logic gates, energy savings may be achieved. Reducing garbage output and ancilla inputs is a primary emphasis of this study, which aims to lower power consumption in reversible multiplexers. Multiplexers with switchable 2:1, 4:1, and 8:1 ratios may be built using the SJ gate and other simple reversible logic gates. The number of ancilla inputs has been cut in half from four to zero, and the amount of garbage output has been cut in half as well, from eight to three, making the 2:1 multiplexer an improvement over the prior design. New 4:1 multiplexer has 10' ancilla inputs, up from 2' in the previous designs. The proposed 4:1 multiplexer also cuts waste production in half from the current 5-to-6 bins per day. The 8:1 multiplexer has two ancilla inputs and nine trash outputs, while the current architecture only has one of each. The functionality of the VHDL and Xilinx 14.7-coded designs is validated by ISIM simulations

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell andelectrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lowerpower, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer’s central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCA Designer-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area

Reversible Logic Circuit Based Twiddle Factor Generation

An efficient hardware implementation of FFT algorithm become essential one in signal analysis domain, more specifically the twiddle factor calculation in FFT computation plays important role in the speed and efficiency of the complete process. World of computation needs the fast and efficient tools to match the need of present scenario, even though there are many methods proposed the Reversible Logic design became the promising area for improvement of speed and reduces the power consumption to a larger extent. In this paper a reversible logic based implementation of twiddle factor generation is proposed

DESIGN OF NOVEL MULTIPLEXER CIRCUITS IN QCA NANOCOMPUTING

Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilize 16 (0.01μm2), 96 (0.11μm2), and 286 (0.43μm2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%-99% compared to the existing multiplexer circuits