Fully source-coupled logic based multiple-valued VLSI

科研費報告書収録論文(課題番号:12480064・基盤研究(B)(2) ・H12～H14/研究代表者:亀山, 充隆/配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

Wireless Sensor Data Logging System Design

Wireless Sensor Data Logging System Design is a standalone electronic sensor device that captures and stores data through wireless communication. This system comprises two main integrated components; the Radio Frequency module and the Microcontroller based system. The main goal of this project is to design and construct a data logging system that effectively monitors the device's measurement values. In real life applications, most data monitoring system is a passive system. This type of system requires manned guarding on site to manage the devices. Therefore, a standalone data logging system offers a better enhancement system to replace the manned guarding method. The standalone data logger system can be applied by leaving the device alone in any place that requires the measurement of humidity and temperature. These data can be retrieved from EEPROM and transferred to a PC whenever needed by a user. A radio frequency module enables these data travels through wireless transmission medium, whereas the serial communication interface enables communication between the devices and PC. For diverse applications, an alarm system can be implemented if assets and security are the major concerns. The final report presents the development of a data logger system which is an integration of radio frequency module and the microcontroller-based system. The system monitors the device's measurement value via a Graphical User Interface. Basically, the system introduces a RF module to replace the hard wired scheme and produce a dynamic data transmission system. It is geared up with a PICI6F877A microcontroller to drive the outputs besides providing communication between devices and a PC. Overall, the project is the best platform to improve the traditional monitoring system and ignites another innovative invention in the future

Temperature To Digital Converter Design And Measurement

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2016Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2016Bu çalışmada AMS 0.35u CMOS teknolojisinde 12 bitlik bir sıcaklık sayısal dönüştürücü tasalarlandı ve serimi yapıldı. Tasarlanan dönüştürücü Euro Practice aracılığıyla İTÜ VLSI Labs finans desteği ile üretildi. Dönüştürücünün yonga boyutları 1024um X 600um 0.6144 mm2 iken giriş çıkış padleri ve ESD elamanlar ile birlikte toplamda 1.43 mm2 alan kaplamaktadır. Simulasyon sonuçları ile -40C 85C sıcaklık aralığıda 12 bitlik 0.25C çözünürlük gösterilmiş ve ölçüm sonuçları ile yine aynı sıcaklık aralığında 10 bitlik 1C çözünürlük doğrulanmıştır.Temperature to digital converter is designed and taped-out using AMS035HB4 process. The dimension of the IC core is 1024um X 600um while full chip with esd and pad rings occupying 1024um X 1395um. The simulation results show that 12 bits temperature to digital conversion is achieved with 0.25C resolution while measurement verifies 10 bits temperature to digital conversion with 1 C resolution.Yüksek LisansM.Sc

Sistema de gestió domòtica per optimitzar el consum energètic d’un habitatge

Des de fa anys, la societat ha viscut diversos canvis tecnològics en àmbits com: l’electrònica, les telecomunicacions, la informàtica, l’arquitectura i l’automàtica. Aquesta evolució, ha portat com a resultat el concepte d’edifici intel·ligent. L’objectiu d’aquest projecte és dissenyar un sistema domòtic, mitjançant l’electrònica, que permeti reduir el consum energètic d’un habitatge convencional. Actualment, podem trobar diferents sistemes a l’hora de realitzar un habitatge domòtic, però tots ells estan basats en la combinació i connexió de tres elements bàsics; controladors, sensors i actuadors. Al llarg de la memòria es desenvolupa a nivell teòric: què és la domòtica i quines característiques poden tenir els diversos sistemes, també s’exposaran diversos conceptes sobre l’estalvi energètic. A continuació, es realitza el dimensionat d’un habitatge unifamiliar de 107 m2 i les seves instal·lacions. Aquest ens permet, posteriorment, comparar l’estudi energètic convencional amb el del mateix habitatge un cop implementat un sistema domòtic capaç d'actuar sobre els sistemes d'il·luminació, persianes, tendal, clima, connexió d'electrodomèstics, alarmes, reg i escenes de l'habitatge. D’aquesta manera, comprovar si hi ha un posterior estalvi en el consum. També es valoren possibles canvis pel que fa a les fonts d’energia, amb el mateix objectiu; augmentar l’eficiència energètica de l’habitatge. Finalment, es presenta un sistema domòtic que basa el seu funcionament en un microcontrolador Peripheral Interface Controller (PIC). I que es desenvolupa amb l’objectiu de poder controlar tots els sistemes que consumeixen energia de l’habitatge, gràcies als diversos sensors i actuadors. A més a més, es dissenya una petita aplicació mòbil que es connectarà via Bluetooth a la instal·lació domòtica. Això, permetrà a l'usuari actuar sobre el sistema, de la mateixa forma que es fa des de la interface física de controlador central, però d'una forma remota, intuïtiva i per tant més còmoda pel consumidor

A Setup for Testing of Silicon Pixel Modules for the ITk Tracker in the ATLAS Experiment at CERN

New pixel sensors will be installed to the new Inner Tracker upgrade at the ATLAS detector. These sensor will have higher radiation tolerance than the ones currently on the Inner Detector. This thesis will concentrate on development of a test setup dedicated to testing the new pixel sensors. The Peltier Controller Temperature Monitor has been developed for this purpose. IV-curve measurements have also been done on RD53A sensor modules. The Peltier Controller Temperature Monitor has been successfully used in stage 1 qualification test of module testing in the University of Bergen. The Peltier Controller has also been proven to work quite well.Masteroppgave i fysikkPHYS399MAMN-PHY

Space vehicle Viterbi decoder

The design and fabrication of an extremely low-power, constraint-length 7, rate 1/3 Viterbi decoder brassboard capable of operating at information rates of up to 100 kb/s is presented. The brassboard is partitioned to facilitate a later transition to an LSI version requiring even less power. The effect of soft-decision thresholds, path memory lengths, and output selection algorithms on the bit error rate is evaluated. A branch synchronization algorithm is compared with a more conventional approach. The implementation of the decoder and its test set (including all-digital noise source) are described along with the results of various system tests and evaluations. Results and recommendations are presented

AUTOMATED GUIDED ROBOT (AGR)

This project concerns the design and fabrication of the Automated Guided Robot (AGR) prototype, utilizing artificial intelligence (AI) and genetic algorithm (GA) as a mainframe in helping the robot to generate a self-understanding of the area of work and mobilization to a destination desired by the user. The main objective of this project is to create and develop a Path Planning Mobile Robot able to avoid obstacles in its path and reach a target designated position from its starting point utilizing 3 wheel-based rover body, sensors, linear motors and microcontrollers. Compared to manual mobile robots, AGRs require sensors and control systems that generate feedback for the re-evaluation of an unexpected situation and to detect obstacles in the path the AGR is required to follow. The paper describes the network algorithms developed and used in the design process of the AGR including simulations and circuit designs done for the prototype. A general robotics circuit construction of the mainframe target board for central processing, a controller board for the sensor feedbacks and a small base tri-wheeled structure has been fabricated by the author and continual troubleshooting and enhancement has been done for these components of the AGR. Algorithm conversion to C code programming has been done throughout the project for the obstacle avoidance and path planning algorithms based upon the GA platform ofAI

VFAT2: A front-end system on chip providing fast trigger information, digitized data storage and formatting for the charge sensitive readout of multi-channel silicon and gas particle detectors

The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal calibration, intelligent “fast OR” trigger building outputs, digital data tagging and storage, data formatting and data packet transmission with error protection. VFAT2 is designed to work in the demanding radiation environments posed by modern H.E.P. experiments and in particular the TOTEM experiment of the LHC. Measured results are presented demonstrating full functionality and excellent analog performance despite intensive digital activity on the same piece of silicon