A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A Multiband Low Noise Amplifier for Software Defined Radio Using Switchable Active Shunt Feedback Input Matching

Radio frequency (RF) receivers are the key front-end blocks in wireless devices such as smartphones, pagers, PDAs etc. An important block of the RF receiver is the Low-noise amplifier. It’s function is to amplify with little noise addition, the RF signal received at the atenna. Modern wireless devices for example the smartphone, incorporates multiple functionalities supported by various RF standards- GPS, Bluetooth, Wifi, GSM etc. Thus, the current trend in the wireless technology is to integrate radio receivers for each RF standard into a single system-on-chip (SoC) in order to reduce cost and area of the devices. In view of this, multiband RF receivers have been developed which feature multiband LNAs. This thesis presents the design and implementation of a multiband LNA for Software Defined Radio Applications. In this thesis, basic radio-frequency concepts are discussed which is followed by a discussion of pros and cons of various multistandard low-noise amplifier topologies. This is then followed by the design of the proposed reconfigurable LNA. The LNA is designed and fabricated in IBM 0.18um CMOS technology. It is made up of dual LC resonant tanks, one to switch between 5.2GHz and 3.5GHz frequency bands and the other, to switch between 2.4GHz and 1.8GHz bands. The input matching of the LNA is achieved using a switchable shunt active feedback network. The LNA achieves S21 of between 10.1dB and 13.43dB. It achieves an input matching (S11) between -13.44 dB and -11.97 dB. The noise figure measured ranges from 2.8 dB to 4.3 dB. The LNA also achieves an IIP3 from -7.12 dBm to -3.45 dBm at 50 MHz offset. The power consumption ranges from 7 mW to 7.2 mW

Apport de l'échantillonnage aléatoire à temps quantifié pour le traitement en bande de base dans un contexte radio logicielle restreinte

The work presented in this Ph.D. dissertation deals with the design of multistandard radio receivers that process signals with heterogeneous specifications. The originality of these research activities comes from the application of random sampling at the baseband stage of a software defined radio receiver. The purpose behind the choice of random sampling is to take advantage of its alias-free feature. The originality of this work is the analytic proof of the alias attenuation feature of the time quantized random sampling, the implementation version of the random sampling. A second contribution concerns also the analytic study of the simplest implementation version of the random sampling, the time quantized pseudo-random sampling (TQ-PRS). Theoretical formulas allow the estimation of the alias attenuation in terms of time quantization factor and oversampling ratio. Alias attenuation measurement permits to design the baseband stage of the proposed multistandard radio receiver architecture. The design concerns different configuration of the baseband stage according to the performances of the used analog-to-digital converters (ADC). The TQPRS allows decreasing the anti-aliasing filter order or the sampling frequency. The design of the baseband stage reveals a difference on the choice of the time quantization factor for each standard. The power consumption budget analysis demonstrates a power consumption gain of 30% regarding the power consumption of the analog baseband stage. This gain becomes 27.5% when the TQ-PRS clock and the digital canal selection stages are considered.Ces travaux de recherche s’inscrivent dans le cadre de la conception de récepteurs multistandard optimisés pouvant traiter des signaux à spécifications hétérogènes. L’idée est d’appliquer l’échantillonnage aléatoire au niveau de l’étage en bande de base d’un récepteur radio logicielle restreinte afin de tirer profit de son pouvoir d’anti-repliement. La nouveauté dans ces travaux est l’étude analytique de la réduction du repliement spectral par l’échantillonnage aléatoire à temps quantifié, candidat favorable à l’implémentation matérielle. Une deuxième contribution concerne aussi l’étude analytique de l’échantillonnage pseudo-aléatoire à temps quantifié (TQ-PRS) dont l’importance réside en sa grande facilité d’implémentation matérielle. Les formulations théoriques ont permis d’estimer l’atténuation des répliques en fonction du facteur de la quantification temporelle et du facteur du sur-échantillonnage. Les mesures de l’atténuation du repliement spectral ont permis de dimensionner l’étage en bande de base d’une architecture de réception multistandard. Le dimensionnement s’intéresse à différentes configurations de l’étage en bande de base régies par les performances du convertisseur analogique numérique (ADC) utilisé.Les travaux de recherche ont démontré que l’application du TQ-PRS au niveau de l’ADC mène soit à une réduction de l’ordre du filtre anti-repliement soit à une réduction de la fréquence d’échantillonnage. Un bilan global de la consommation de puissance a permis un gain de 30% de la consommation de l’étage en bande de base analogique. En tenant compte du générateur de l’horloge TQ-PRS et de l’étage de sélection numérique du canal, ce gain devient 25%

Concurrent multiband direct RF sampling receivers

Direct radio frequency (RF) sampling receivers are investigated for use in concurrent multiband reception for mobile broadband (MBB) applications. The recent proliferation of different frequency bands and standards in wireless communications has allowed large increases in mobility and throughput, but the number of receivers in a device is limited by physical space and power consumption. Software Defined Radio (SDR) is increasingly being explored to reduce the number of analog RF components required. This paper examines the use of direct RF digitization, allowing tunable and concurrent reception of multiple bands with a single RF front-end. Full mathematical models of both Nyquist and subband sampling receivers are presented and used to investigate a quadband LTE receiver, which is modeled in Simulink and implemented in a hardware-in-the-loop (HWIL) testbed. Individual bands are simulated to have at worst -95dBm sensitivity for 16-QAM with Nyquist sampling and -83dBm with subband sampling. Desensitization of the receivers due to multiband processing is evaluated theoretically and experimentally, showing a maximum of 3dB degradation, which is within the LTE standard for adjacent band interference

Architecture d'amplificateur faible bruit large bande multistandard avec gestion optimale de la consommation

In recent years, the sustainable development, especially the control of the electrical appliances' consumption, has became a major issue in our society. The optimisation of each electrical devices' energy is needed to reduce the consumption of home appliances. The objective of this thesis is the realization of a low noise amplifier (LNA) that offers two modes of operation depending on the quality of the received signal: a high performance mode and a low consumption mode.In order to meet the problem related to multistandard systems, the distributed architecture is selected for low noise amplifier. Indeed, it is known for its wide bandwidth and tunable power gain. A design method is proposed, which is based on GaAs technology of TriQuint Semiconductor Texas foundry. The LNA's high performance mode measurement results is at the level of the state of the art. For the low consumption mode, LNA shows good performance while reducing power consumption by 91%.Finally, an innovative reconfiguration strategy is defined. It's applied to a homodyne receiver based on the integration of our LNA. It reduces significantely the receiver's consumption in case where the received power allows the receiver operates in low power mode (constraint of the Bit Error Rate (BER) is verified). Considering each received power is equiprobable, our reconfigurable receiver saves consumption by 77% compared to a conventional receiver that has a single mode (high performance mode).Ces dernières années, le développement durable, notamment le contrôle de la consommation de nos appareils électriques, est devenu un enjeu majeur de notre société. L'essor de la domotique associé à cette problématique implique la nécessité d'optimiser le bilan énergétique de chaque dispositif électrique. L'objectif de cette thèse est la réalisation d'un amplificateur faible bruit (LNA) qui propose deux modes de fonctionnement suivant la qualité du signal reçu: un mode haute performance et un mode basse consommation.Afin de satisfaire la problématique liée aux systèmes multistandard, l'architecture sélectionnée pour l'amplificateur faible bruit est la topologie distribuée. En effet, elle est connue pour ses performances en terme de bande passante et permet un gain en puissance accordable. Une méthode de conception est proposée, basée sur la technologie GaAs de la fonderie TriQuint Semiconducteur Texas. Les mesures réalisées sur le LNA dans sa configuration haute performance se situe au niveau de l'état de l'art. Pour le mode basse consommation, on obtient de bonnes performances tout en réduisant sa consommation de 91%.Enfin, une stratégie de reconfiguration innovante est proposée basée sur l'intégration de notre LNA dans un récepteur homodyne. Elle permet de réduire de manière significative la consommation du récepteur, dans le cas où la puissance reçue permet un fonctionnement en mode basse consommation (contraintes sur le Bit Error Rate (BER) vérifiées). En considérant chaque puissance reçue de manière équiprobable, notre récepteur reconfigurable a une consommation réduite de 77% par rapport à un récepteur classique qui possède un seul mode de fonctionnement (mode haute performance)

CMOS Low-Noise Amplifier Design for Reconfigurable Mobile Terminals

Kommunikationsstandards aus Europa, Japan und den USA sind mit einander nicht kompatibel. Das ist einen Nachteil besonders in der Mobiltelefonie, wo es bisher keinen allgemeinen Standard gibt. Die Vielzahl an Funkstandards führt zu einigen Nachteilen, deshalb scheint das Bedürfnis für Rekonfigurierbarkeit offensichtlich zu sein. Ein rekonfigurierbares Terminal sollte im Stande sein, verschiedene Standards zu unterstützen. Die vernünftige Integration von verschiedenen Standards kann Standards einschließen, die derselben Familie (z.B. GSM) gehören, aber in verschiedenen Kontinenten entwickelt werden. Solche Terminals existieren bereits und ein breites Angebot besteht auf dem Markt. Ein ziemlich neuer Ansatz der Standardintegration ist die Kombination von verschiedenen Familien von Standards, zum Beispiel zwischen drahtloser Datenübertragung wie UMTS mit WLAN oder HIPERLAN. In diesem Fall sind fast alle Parameter, die einen Standard definieren, verschieden. In dieser Arbeit wird ein rekonfigurierbares Multistandard Terminal betrachtet, das sowohl OFDM basierte WLAN Standards (IEEE802.11 und Hiperlan/2) als auch den CDMA basierten UMTS FDD unterstützt. Besondere Aufmerksamkeit galt dem Empfänger dieses Terminals. Eine rekonfigurierbare hybride Architektur ist ausstelle einer Architektur entwickelt worden, die mehrere Parallele umschaltbare Sender-Empfänger verwendet. Zusätzlich zur hybriden Architektur werden die negativen Einflüsse des HF-Teils auf die Empfänger-Performance untersucht. Der zweite Teil dieser Arbeit behandelt Transistor-Physik und den Entwurf eines rauscharmen Verstärkers für einen rekonfigurierbaren Empfänger, wie oben beschrieben. Da die kleinen FET-Größen aktuellen submikrometer RF-MOS-Technologien niedrige Kapazitätswerte haben, sind große Induktivitäten für die Anpassung erforderlich. Wegen ihre großen Abmessungen werden sie außerhalb des ICs realisiert. Deshalb kann die Pad-Kapazität im Designprozess nicht länger vernachlässigt werden. Es wird gezeigt, dass die Rauschzahl von rauscharmen Verstärkern wesentlich durch die richtige Wahl von passiven Systemkomponenten verbessert werden kann. Eine Designmethodik wird eingeführt, die den equivalenten Rauschwiderstand reduziert, und dadurch sehr gutes Rauschverhalten trotz relativ schlechte Rauschanpassung erreichen kann. Die Messungen des Verstärkers hinsichtlich Rauschverhalten und Stromverbrauch, zeigen sehr gute Ergebnisse. Sie gehören zu den besten überhaupt bekannten. 0.76 dB-Rauschzahl und 12 dB Gewinn wurden bei 2.14 GHz erreicht, bei 3.5 mA Stromverbrauch und 1.2V Betriebsspannung.Communication standards developed in Europe, Japan and USA are not compatible with each other. This is a profound drawback particularly in the digital cellular telephony, where there is no common standard up to now. The variety of wireless standards leads to some disadvantages, therefore the need for reconfigurability seems to be evident. A reconfigurable terminal should be able to support different standards. Reasonable integration of different standards may include standards, which belong to the same family (e.g., GSM), but are developed in different continents. Such terminals have been already produced and a broad offer exists on the market. A rather new approach of the standard integration is the combination of different families of standards, for example between wireless data and digital cellular telephony like UMTS with WLAN or HIPERLAN. In this case, nearly all parameters defining a standard are different. In the scope of this work the multistandard, reconfigurable terminal is considered that supports the OFDM based WLAN standards (IEEE802.11 and Hiperlan/2) and the CDMA based UMTS FDD standard. Special consideration has been made for the receiver of this terminal. A reconfigurable hybrid architecture has been developed, rather than an architecture using many parallel switchable transceivers. Additionally to the hybrid architecture, a study on RF impairments is given. The second part of this work handles with transistor physics and low noise amplifier design for a reconfigurable receiver, defined earlier. Since the small FET sizes of state of the art sub-micron RF-MOS-technologies have low capacitance values, thus large inductors are needed for matching. Because of theirs large dimensions they are placed off-chip. For this reason, the pad capacitance can not be longer neglected in the design process. % It is shown that the noise figure of low-noise amplifiers can be improved considerably by a proper choice of passive components. A design methodology is introduced, which reduces the equivalent noise resistance, and thus very good noise performance can be achieved in spite of rather poor noise matching. The measurements of the amplifier, in respect to the noise performance and power consumption, show very good results, one of the best ever reported. 0.76 dB noise figure and 12 dB gain were achieved at 2.14~GHz, 3.5 mA supply current and 1.2 V supply voltage

Linearity vs. Power Consumption of CMOS LNAs in LTE Systems

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) system. Using proposed figure of merit to compare 35 state-of-the-art LNA circuits published in recent years, the paper shows a proportional but relatively weak dependence between amplifier performance (that is combined linearity, noise figure and gain) with power consumption. As a result, the predicted increase of LNA performance, necessary to satisfy stringent linearity specifications of LTE standard, may require a significant increase in power, a critical budget planning aspect for both handheld devices and base stations operating in small cells

Subsampling receivers with applications to software defined radio systems

Este trabajo de tesis propone la utilización sistemas basados en submuestreo como una alternativa para la implementación de la etapa de down-conversion de los receptores de radio frecuencia (RF) empleados para aplicaciones multi-estándar y SDR (Software Defined Radio). El objetivo principal será el de optimizar el diseño en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el número de componentes al mínimo es clave cuando un mismo receptor procesa diferentes estándares de comunicación, las arquitecturas basadas en submuestreo han sido seleccionadas, donde la reusabilidad de los componentes empleados es posible, así como la reducción de los costes totales de los receptores de comunicación y de los equipos de certificación que emplean estas arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topología del receptor. Como la idea de la tecnología SDR es implementar todas las funcionalidades del receptor (filtrado, amplificación) en el dominio digital, el convertidores analógico-digital (ADC) deberá estar localizado en la cadena de recepción lo más cerca posible a la antena, siendo el objetivo final el convertir la señal directamente de RF a digital. Sin embargo, con los actuales ADC no es posible implementar esta idea debido al alto ancho de banda que necesitarían sin perder resolución para cubrir las especificaciones de los estándares de comunicaciones inalámbricas. Por tanto, los sistemas basados en submuestreo se presentan como la opción más adecuada para implementar este tipo de sistemas debido a que pueden muestrear la señal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la elección de la frecuencia de muestreo. De este modo, los requerimientos del ADC serán relajados ya que, usando estas arquitecturas, este componente procesará la señal a frecuencias intermedias. Una vez se han introducido los conceptos principales de las técnicas de submuestreo, esta tesis doctoral presenta el diseño de una tarjeta de adquisición de datos basada en submuestreo con la finalidad de ser implementada como un receptor de test y certificación de banda ancha. El sistema propuesto proporciona una alta resolución para un elevado ancho de banda, a partir del uso de un S&H de bajo jitter y de un convertidor analógico digital ADC que trabaja a frecuencias intermedias. El sistema es implementado usando dispositivos comerciales en una placa de circuito impreso diseñada y fabricada, y cuya caracterización experimental muestra una resolución de más 8 bits para un ancho de banda analógico de 20 MHz. Concretamente, la resolución medida será mayor de 9 bits hasta una frecuencia de entrada de 2.9 GHz y mayor de 8 bits para una frecuencia de entrada de hasta 6.5 GHz, lo cual resulta suficiente para cubrir los requerimientos de la mayor parte de los actuales estándares de comunicaciones inalámbricas (GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX). Sin embargo, los receptores basados en submuestreo presentan algunos importantes inconvenientes, como son adicionales fuentes de ruido (jitter y plegado de ruido térmico) y una dificultad añadida para implementarlo en escenarios multi-banda y no lineales. Acerca del plegado de ruido en la banda de interés, esta tesis propone el uso de una técnica basada en una arquitectura de reloj múltiple con el objetivo de aumentar la resolución y cubrir un número mayor de estándares para su test y certificación. Empleando una frecuencia de muestreo mayor para el caso del S&H, se conseguirá reducir este efecto, aumentando la resolución en aproximadamente 0.5-1 bit respecto al caso de sólo usar una fuente de reloj. Las expresiones teóricas de esta mejora son desarrolladas y presentadas en esta tesis, siendo posteriormente corroboradas de modo experimental. Por otra parte, esta tesis también propone novedosas técnicas para la aplicación de estos sistemas de submuestreo en entornos multi-banda y no lineales, los cuales presentan desafíos adicionales por el hecho de existir la posibilidad de solapamiento entre la señal de interés y los otros canales de comunicación, así como de solapamiento con sus armónicos. De este modo, esta tesis extiende el uso de los sistemas basados en submuestreo para este tipo de entornos, proponiendo técnicas para la elección de la frecuencia óptima de muestreo que evitan el solapamiento entre señales, a la vez que consiguen incrementar la resolución del receptor. Finalmente, se presentará la optimización en cuanto a características de ruido de un receptor concreto para aplicaciones de banda dual en entornos no lineales. Dicho receptor estará basado en las técnicas de reloj múltiple presentadas anteriormente y en una estructura de multi-filtro entre el S&H y el ADC. El sistema diseñado podrá emplearse para diversas aplicaciones a ambos lados de la cadena de comunicación, tal como en receptores de detección de espectro para radio cognitiva, o implementando el bucle de realimentación de un transmisor para la linealización de amplificadores de potencia. Por tanto, la presente tesis doctoral cuenta con tres contribuciones diferenciadas. La primera de ellas es la dedicada al diseño de un prototipo de recepción multi-estándar basado en submuestreo para aplicaciones de test y certificación. La segunda aportación es la dedicada a la optimización de las especificaciones de ruido a partir de las técnicas presentadas basadas en reloj múltiple. Por último, la tercera contribución principal es la relacionada con la extensión de este tipo de técnicas a sistemas multi-banda en entornos no lineales. Todas estas contribuciones han sido estudiadas teóricamente y experimentalmente validadas

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively