Secure Virtualization and Multicore Platforms State-of-the-Art report

SVaM

Fine-grained Energy / Power Instrumentation for Software-level Efficiency Optimization

In the pursuit of both increased energy-efficiency, as well as high-performance, architects are constructing increasingly complex Systems-on-Chip with a variety of processor cores and DMA controllers. This complexity makes software implementation and optimization difficult, particularly when multiple independent applications may be running concurrently on such a heterogeneous platform. In order to take full advantage of the underlying system, increased visibility into the interaction between the software and hardware is needed. This paper proposes on-line and off-line fine-grained instrumentation of SoC components in hardware (e.g. as part of the debug & trace infrastructure) in order to enable improvements and optimization for energy efficiency to be undertaken at higher levels of abstraction, i.e. the programmer and runtime scheduler. Energy counters are incorporated for each component that keep track of energy use. These counters are indexed by customer number tags, that are used to distinguish between the transactions executed on any given component by client applications running in a multitasking SoC environment. The contents of the counters for each augmented component, correlated with the appropriate consumer-numbers, are extracted from a running SoC under test via existing debug & trace interfaces like GDBserver, JTAG and various proprietary trace probes. In addition, auxiliary processing on-chip computes local and global energy figures and offers them through a 4-layer abstraction stack so that programmer-level finegrained energy measurement is made available. Both the O/S scheduler and programmers can adapt their policies and coding styles for their desired energy/performance tradeoff

Dynamic Power Management of High Performance Network on Chip

With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication paradigm to solve this by using highly scalable and efficient packet switched network. The addition of intelligent networking on the chip adds to the chip’s power consumption thus making management of communication power an interesting and challenging research problem. While VLSI techniques have evolved over time to enable power reduction in the circuit level, the highly dynamic nature of modern large SoC demand more than that. This dissertation explores some innovative dynamic solutions to manage the ever increasing communication power in the post sub-micron era. Today’s highly integrated SoCs require great level of cross layer optimizations to provide maximum efficiency. This dissertation aims at the dynamic power management problem from top. Starting with a system level distribution and management down to microarchitecture enhancements were found necessary to deliver maximum power efficiency. A distributed power budget sharing technique is proposed. To efficiently satisfy the established power budget, a novel flow control and throttling technique is proposed. Finally power efficiency of underlying microarchitecture is explored and novel buffer and link management techniques are developed. All of the proposed techniques yield improvement in power-performance efficiency of the NoC infrastructure

Novel development of distributed manufacturing monitoring systems to support high cost and complexity manufacturing

In the current manufacturing environment, characterized by diverse change sources (e.g. economical, technological, political, social) and integrated supply chains, success demands close cooperation and coordination between stakeholders and agility. Tools and systems based on software agents, intelligent products and virtual enterprises have been developed to achieve such demands but either because of: (i) focus on a single application; (ii) focus on a single product; (iii) separation between the product and its information; or (iv) focus on a single system characteristic (e.g. hardware, software, architecture, requirements) their use has been limited to trial or academic scenarios. In this thesis a reusable distributed manufacturing monitoring system for harsh environments, capable of addressing traceability and controllability requirements within stakeholders and across high cost and complexity supply chains is presented. [Continues.

Quarc: an architecture for efficient on-chip communication

The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems. Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm. By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmission commences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence. To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation of the building blocks of the architecture, including topology, router and network interface. The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture. Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication

Ethical implication of emerging technologies

Titre de l'écran-titre (visionné le 3 mai 2007

The use of prepaid cards for banking the poor

Prepaid products can become an effective instrument for banking the poor, as they can be used for collecting microdeposits and so operate as a low-cost account. Prepaid platforms have characteristics that make them especially useful for developing low-cost microfinance business models. Indeed, customers using prepaid systems do not need bank accounts or debit or credit cards. Prepaid issuers do not need to develop or invest in new technologies, as this mechanism can be used on a range of platforms, including PCs, mobile phones, hand-held and set-top boxes. Furthermore, prepaid products are specially designed for offering services demanded by the poor, such as micropayments, microdeposits and even microcredits. Lastly, they allow users to monitor their cash flow by receiving statements (some providers offer this feature online, others provide physical statements) or accessing balances through PCs, mobile phones, hand-held and set-top boxes. Besides collecting microdeposits, prepaid products (or SVCs as they are called in the United States) offer other services that can be very valuable for serving the unbanked population. As explained in this paper, prepaid products generally lack the identification and credit requirements that effectively bar millions of individuals from opening traditional bank accounts, especially in the United States. Moreover, prepaid products can be purchased and reloaded at a growing number of locations other than bank branches, such as check cashers, convenience stores and other retailers. Prepaid instruments can also provide immediate availability of funds at a cost that, in some cases, is lower than other alternatives for unbanked consumers. Also, prepaid products are difficult to overdraw, thus reducing the likelihood of unexpected fees. Lastly, many prepaid issuers offer some sort of bill pay option, especially branded cards that enable signature-based transactions, and a significant number of them offer remittances.Prepaid card; microdeposits; mobile phone; store value card; e-money; banking the poor;

Design and implementation of a modular controller for robotic machines

This research focused on the design and implementation of an Intelligent Modular Controller (IMC) architecture designed to be reconfigurable over a robust network. The design incorporates novel communication, hardware, and software architectures. This was motivated by current industrial needs for distributed control systems due to growing demand for less complexity, more processing power, flexibility, and greater fault tolerance. To this end, three main contributions were made. Most distributed control architectures depend on multi-tier heterogeneous communication networks requiring linking devices and/or complex middleware. In this study, first, a communication architecture was proposed and implemented with a homogenous network employing the ubiquitous Ethernet for both real-time and non real-time communication. This was achieved by a producer-consumer coordination model for real-time data communication over a segmented network, and a client-server model for point-to-point transactions. The protocols deployed use a Time-Triggered (TT) approach to schedule real-time tasks on the network. Unlike other TT approaches, the scheduling mechanism does not need to be configured explicitly when controller nodes are added or removed. An implicit clock synchronization technique was also developed to complement the architecture. Second, a reconfigurable mechanism based on an auto-configuration protocol was developed. Modules on the network use this protocol to automatically detect themselves, establish communication, and negotiate for a desired configuration. Third, the research demonstrated hardware/software co-design as a contribution to the growing discipline of mechatronics. The IMC consists of a motion controller board designed and prototyped in-house, and a Java microcontroller. An IMC is mapped to each machine/robot axis, and an additional IMC can be configured to serve as a real-time coordinator. The entire architecture was implemented in Java, thus reinforcing uniformity, simplicity, modularity, and openness. Evaluation results showed the potential of the flexible controller to meet medium to high performance machining requirements