A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters

The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams. However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency. In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary. In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed. Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 $\mu m$ SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 2$\times$2 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature. In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class $F^{-1}$ power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm. Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas

CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

Next Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2

Amplificadores de potência para radiofrequência insensíveis à impedância de carga

Solid state power amplifiers (SSPAs) evolved significantly over the last few decades, mainly, due to the use of new transistor technologies, such as gallium nitride (GaN) high-electron-mobility transistors (HEMTs), very advanced computer-aided design (CAD) software, and very effective digital pre-distortion (DPD) algorithms. This led to a considerable performance improvement, in terms of energy efficiency, output power, and linearity. To achieve this performance, power amplifier (PA) designers normally push the used transistors very close to their physical safe operating limits, and consider them to operate for a fixed output load. However, the designed PAs are used for many different industrial and/or telecommunication applications, and, in some cases, such as, for example, microwave cooking or massive multiple-input multiple-output (MIMO) fifth generation (5G) base stations (BSs), the output load of these amplifiers can change. Under this nonoptimal scenario, the used transistors will operate for non-nominal loads, and the PAs performance can be severely degraded. Moreover, in highly optimized designs, where the transistors are operated close to their safe limits, their reliability can be reduced or, in extreme cases, they can even be permanently damaged. Therefore, load insensitive PA architectures, and/or techniques that aim at reducing the load variation seen by the PA, are necessary to improve the performance under load varying scenarios. This thesis presents various strategies to improve load insensitiveness of PAs. The presented techniques are based on tunable matching networks (TMNs) and on the amplifiers’ drain supply voltage (VDS) variation. The developed TMNs successfully reduced the load variation seen by the PA, and its performance was greatly improved, for non-optimal loading, by also using the derived load dependent VDS variation. These different approaches were tested and validated on single-ended PAs and then, based on their advantages and disadvantages, the most promising technique – the supply voltage modulation – was selected for the design of a Doherty power amplifier (DPA), which is of paramount importance for telecommunication applications. Moreover, since in some applications the output load variation can be unpredictable, we also developed a complete quasi-load insensitive (QLI) PA system that includes an impedance tracking circuit and an automatic real-time compensation of the amplifier performance.Os amplificadores de potência de estado sólido (SSPAs) evoluíram significativamente nas últimas décadas, principalmente devido à utilização de novas tecnologias de transístores, como os transístores de alta mobilidade (HEMTs) de nitreto de gálio (GaN), de ferramentas muito avançadas de projeto assistido por computador (CAD) e de algoritmos de pré-distorção digital (DPD) muito evoluídos. Isto levou a uma melhoria de desempenho considerável, em termos de eficiência energética, potência de saída e linearidade. Normalmente, para obter estes níveis de desempenho, os engenheiros projetam os amplificadores permitindo que os transístores utilizados operem muito perto do seu limite físico de funcionamento seguro e considerando que vão operar para uma carga fixa. No entanto, os amplificadores projetados são utilizados em diversas aplicações industriais e/ou telecomunicações e, em alguns casos, como por exemplo fornos micro-ondas ou estações base 5G, a sua carga de saída pode variar devido a várias causas, que podem ser previsíveis ou imprevisíveis. Neste cenário não ideal, os transístores utilizados operam para cargas não ótimas e o desempenho dos amplificadores pode ser muito degradado. Além disso, em projetos muito otimizados, onde os transístores são operados perto do seu limite de funcionamento seguro, a sua durabilidade pode ser reduzida ou, em casos extremos, podem até ser permanentemente danificados. Portanto, para melhorar o desempenho dos amplificadores em cenários de carga variável, são necessárias novas arquiteturas e/ou técnicas que visam reduzir a variação da carga vista pelos transístores utilizados. Esta tese apresenta várias estratégias para melhorar a insensibilidade dos amplificadores em relação à variação de carga. As técnicas apresentadas são baseadas em malhas de adaptação dinâmicas (TMNs) e na variação da tensão de alimentação dos amplificadores. As malhas de adaptação desenvolvidas permitiram reduzir a variação de carga vista pelo amplificador e a variação da sua tensão de alimentação permitiu melhorar o desempenho para operação com cargas não ótimas. Estas abordagens foram testadas e validadas em amplificadores baseados num só transístor, e, posteriormente, com base nas suas vantagens e desvantagens, a técnica mais promissora – a modulação da tensão de alimentação – foi selecionada para o projeto de um amplificador Doherty, que é imprescindível para telecomunicações. Além disso, como em algumas aplicações a variação da carga de saída pode ser imprevisível, também desenvolvemos um sistema completo que inclui um circuito de medida de impedância e compensação do desempenho do amplificador em tempo real.Programa Doutoral em Engenharia Eletrotécnic

III-V Nanowire MOSFET High-Frequency Technology Platform

This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Conception et réalisation de fonctions millimétriques en technologie BiCMOS 55nm

In the past few years, the feasibility of high performance millimeter-wave(mmWave) fully-integrated transceivers has been widely demonstrated in both CMOS andBiCMOS silicon technologies. Nowadays, automatic level control (ALC) solutions and in-situtesting (BIT: Built in Testing) and characterization of mmWave components, constitute themajor research interest in mmWave domain. This work focus on the development of the mainbuilding blocks (power detectors and baluns) that meet the requirement of the today’smmWave ALC and BIT applications. The developed prototypes take advantage of the highperformances transistors offered by the BiCMOS 55 nm technology, from STMicroelectronics, aswell as the high performances of the slow-wave based passive components developed by theIMEP-LAHC laboratory. Several prototypes were developed as a proof of concept for thedesignated applications. This work helps future generation millimeter-wave systems to havefaster development and better robustness.Au cours des dernières années, la faisabilité des émetteurs-récepteurs millimétriques entièrement intégrés a été largement démontrée en technologies silicium CMOS et BiCMOS. Deux axes sont actuellement très porteurs dans ce domaine : (1) l’amélioration des performances à travers des boucles d’asservissement intégrées (ALC : Automatique Level Control), (2) le développement de solutions de caractérisation sur silicium des composants millimétriques (BIT : Built In Test). L’objectif principal de cette thèse est de développer les blocsde base (détecteurs de puissance et baluns) pour répondre aux besoins actuels des applications ALC et BIT. Les circuits réalisés combinent l’avantage de composants actifs de la technologie BiCMOS 55 nm, de STMicroelectronics, avec l’avantage des structures passives à ondes lentes développées à l’IMEP-LAHC. Ce travail permet un développement plus rapide et robuste pour la future génération de systèmes millimétriques