System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Bridges Structural Health Monitoring and Deterioration Detection Synthesis of Knowledge and Technology

INE/AUTC 10.0

Design and Implementation of the Quadrature Voltage Controlled Oscillator for Wireless Receiver Applications Utilizing 0.13 {Lm and 0.18 {Lm Deep Sub-Micron RF CMOS Technology

The field of high-frequency circuit design is receiving significant industrial attention due to variety of radio frequency and microwave applications. This work proposes the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) for wireless receiver applications. An enhanced investigation and design of the low power, low phase noise and low phase error quadrature voltage controlled oscillator (LP3 - QVCO) is carried out in comparison to conventional LC- QVCO. The design, implementation and characterization of the complementary LP3 - QVCO is carried out with the integration of 40 S1 source damping resistor (Rdmp), tail biasing resistor (Rtait) and multifinger gate width configuration of the pMOS varactors and 50 S1 impedance of common drain output buffers. The LP3 - QV CO implementation is carried out using 0.18 p,m, 6 metal, 1 poly, 1.8 V and 0.13 p,m, 8 metal, 1 poly, 1.2 V deep sub-micron CMOS and RF CMOS process technologies. The three different designs with the center frequencies of 2.8 GHz, 3.1 GHz and 3.8 GHz are implemented using 0.18 p,m CMOS and RF CMOS process technology. The remaining four designs with the center frequencies of 4.35 GHz and 5 GHz are implemented using 0.13 p,m RF CMOS process technologies. The LP3 - QVCO design exhibit the measured phase noise of -110.13 dBc/Hz and -108.54 dBc/Hz at the offset frequency of 1 MHz, with multifinger gate width configuration of pMOS varactor (3.125 p,m x 64 = 200 p,m) and (8 p,m x 25 = 200 p,m), respectively. The phase noise im provement of 1.63 dB is achieved in LP3 - QVCO design implemented with (3.125 I'm x 64 = 200 I'm) mult.ifinger gate width configuration of pMOS varactor in comparison to (8 f.tm x 25 = 200 f.tm). The measured center frequency of the LP3 - QVCO is 4.35 GHz with the frequency tuning range of 4.21 GHz to 4.44 GHz. Both LP3 - QVCO core power dissipation is 3.36 m W from 1.2 V de power supply. The measured phase error is less than 0.2'. The calculated figure of merit (FOM) is -177.6 dBc/Hz. The symmetrical spiral inductor is also used with patterned ground shield (PGS). The quality (Q) factor of inductor is 18.6 and is implemented using 0.13 f.tm RF CMOS process technology

Development of micromachined millimeter-wave modules for next-generation wireless transceiver front-ends

This thesis discusses the design, fabrication, integration and characterization of millimeter wave passive components using polymer-core-conductor surface micromachining technologies. Several antennas, including a W-band broadband micromachined monopole antenna on a lossy glass substrate, and a Ka-band elevated patch antenna, and a V-band micromachined horn antenna, are presented. All antennas have advantages such as a broad operation band and high efficiency. A low-loss broadband coupler and a high-Q cavity for millimeter-wave applications, using surface micromachining technologies is reported using the same technology. Several low-loss all-pole band-pass filters and transmission-zero filters are developed, respectively. Superior simulation and measurement results show that polymer-core-conductor surface micromachining is a powerful technology for the integration of high-performance cavity, coupler and filters. Integration of high performance millimeter-wave transceiver front-end is also presented for the first time. By elevating a cavity-filter-based duplexer and a horn antenna on top of the substrate and using air as the filler, the dielectric loss can be eliminated. A full-duplex transceiver front-end integrated with amplifiers are designed, fabricated, and comprehensively characterized to demonstrate advantages brought by this surface micromachining technology. It is a low loss and substrate-independent solution for millimeter-wave transceiver integration.Ph.D.Committee Chair: John Papapolymerou; Committee Chair: Manos Tentzeris; Committee Member: Gordon Stuber; Committee Member: John Cressler; Committee Member: John Z. Zhang; Committee Member: Joy Laska

Applications of Graphene at Microwave Frequencies

In view to the epochal scenarios that nanotechnology discloses, nano-electronics has the potential to introduce a paradigm shift in electronic systems design similar to that of the transition from vacuum tubes to semiconductor devices. Since low dimensional (1D and 2D) nano-structured materials exhibit unprecedented electro-mechanical properties in a wide frequency range, including radio-frequencies (RF), microwave nano-electronics provides an enormous and yet widely undiscovered opportunity for the engineering community. Carbon nano-electronics is one of the main research routes of RF/microwave nano-electronics. In particular, graphene has shown proven results as an emblematic protagonist, and a real solution for a wide variety of microwave electronic devices and circuits. This paper introduces graphene properties in the microwave range, and presents a paradigm of novel graphene-based devices and applications in the microwave/RF frequency range

Aerospace medicine and biology: A continuing bibliography with indexes, supplement 190, February 1979

This bibliography lists 235 reports, articles, and other documents introduced into the NASA scientific and technical information system in January 1979

SuperCam, a 64-pixel heterodyne imaging array for the 870 micron atmospheric window

We report on the development of SuperCam, a 64 pixel, superheterodyne camera designed for operation in the astrophysically important 870 micron atmospheric window. SuperCam will be used to answer fundamental questions about the physics and chemistry of molecular clouds in the Galaxy and their direct relation to star and planet formation. The advent of such a system will provide an order of magnitude increase in mapping speed over what is now available and revolutionize how observational astronomy is performed in this important wavelength regime. Unlike the situation with bolometric detectors, heterodyne receiver systems are coherent, retaining information about both the amplitude and phase of the incident photon stream. From this information a high resolution spectrum of the incident light can be obtained without multiplexing. SuperCam will be constructed by stacking eight, 1x8 rows of fixed tuned, SIS mixers. The IF output of each mixer will be connected to a low-noise, broadband MMIC amplifier integrated into the mixer block. The instantaneous IF bandwidth of each pixel will be ~2 GHz, with a center frequency of 5 GHz. A spectrum of the central 500 MHz of each IF band will be provided by the array spectrometer. Local oscillator power is provided by a frequency multiplier whose output is divided between the pixels by using a matrix of waveguide power dividers. The mixer array will be cooled to 4K by a closed-cycle refrigeration system. SuperCam will reside at the Cassegrain focus of the 10m Heinrich Hertz telescope (HHT). A prototype single row of the array will be tested on the HHT in 2006, with the first engineering run of the full array in late 2007. The array is designed and constructed so that it may be readily scaled to higher frequencies.Comment: 12 pages, 14 figures, to be published in the Proceedings of SPIE Vol. 6275, "Astronomical Telescopes and Instrumentation, Millimeter and Submillimeter Detectors and Instrumentation for Astronomy III

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Tests with a Carlina-type diluted telescope; Primary coherencing

Studies are under way to propose a new generation of post-VLTI interferometers. The Carlina concept studied at the Haute- Provence Observatory is one of the proposed solutions. It consists in an optical interferometer configured like a diluted version of the Arecibo radio telescope: above the diluted primary mirror made of fixed cospherical segments, a helium balloon (or cables suspended between two mountains), carries a gondola containing the focal optics. Since 2003, we have been building a technical demonstrator of this diluted telescope. First fringes were obtained in May 2004 with two closely-spaced primary segments and a CCD on the focal gondola. We have been testing the whole optical train with three primary mirrors. The main aim of this article is to describe the metrology that we have conceived, and tested under the helium balloon to align the primary mirrors separate by 5-10 m on the ground with an accuracy of a few microns. The servo loop stabilizes the mirror of metrology under the helium balloon with an accuracy better than 5 mm while it moves horizontally by 30 cm in open loop by 10-20 km/h of wind. We have obtained the white fringes of metrology; i.e., the three mirrors are aligned (cospherized) with an accuracy of {\approx} 1 micron. We show data proving the stability of fringes over 15 minutes, therefore providing evidence that the mechanical parts are stabilized within a few microns. This is an important step that demonstrates the feasibility of building a diluted telescope using cables strained between cliffs or under a balloon. Carlina, like the MMT or LBT, could be one of the first members of a new class of telescopes named diluted telescopes.Comment: 18 pages, 17 figures, A&A, accepte