On the self-testing (m,n)-code checker design

We propose an approach to a self-testing (m, n)code checker design, based on subdividing the set of all code words into special subsets called segments. The checker circuit is constructed by using one- and two-output configurable logic blocks (CLB). Previously, in each output of a CLB, a function representing exactly one segment was implemented. In the proposed approach, at each CLBs output, it is possible to implement functions that represent several segments and to provide the self-testing property. It allows reducing the number of CLBs and simplifying the circuit of the checker

Синтез самопроверяемых схем встроенного контроля на основе метода логического дополнения до равновесного кода «2 из 4»

The article explores the peculiarities of self-checking integrated control circuits synthesis by the Boolean complement method based on the "2-out-of-4'' constant-weight code. The article describes the features of integrated control circuits implementation by the Boolean complement method. It is noted that it is possible to synthesize the structures of discrete devices, which have less structural redundancy than in situation of the control circuit implementation by the method of duplication. The effect in structural redundancy reducing is achieved by minimizing the complexity of the control logic block technical implementation and using checkers that are simpler in their structures than the comparator in the system of duplication. The article proposes a method of the integrated control circuit organization based on determining the values of control functions taking into account the maintenance of testability of elements of addition by modulo two in the Boolean complement block and the checker of the "2-out-of-4" code.Исследуются особенности синтеза самопроверяемых схем встроенного контроля по методу логического дополнения на основе равновесного кода «2 из 4». Описываются особенности реализации схем встроенного контроля по методу логического дополнения. Отмечается возможность синтеза структур дискретных устройств, имеющих меньшую структурную избыточность, чем при реализации схемы контроля по методу дублирования. Эффект в снижении структурной избыточности достигается за счет минимизации сложности технической реализации блока контрольной логики и использования более простых по своим структурам тестеров, чем компаратор в системе дублирования. Предлагается способ организации схемы встроенного контроля, основанный на доопределении значений контрольных функций с учетом обеспечения тестируемости элементов сложения по модулю два в блоке логического дополнения и тестера кода «2 из 4»

LSI/VLSI design for testability analysis and general approach

The incorporation of testability characteristics into large scale digital design is not only necessary for, but also pertinent to effective device testing and enhancement of device reliability. There are at least three major DFT techniques, namely, the self checking, the LSSD, and the partitioning techniques, each of which can be incorporated into a logic design to achieve a specific set of testability and reliability requirements. Detailed analysis of the design theory, implementation, fault coverage, hardware requirements, application limitations, etc., of each of these techniques are also presented

Investigations into the feasibility of an on-line test methodology

This thesis aims to understand how information coding and the protocol that it supports can affect the characteristics of electronic circuits. More specifically, it investigates an on-line test methodology called IFIS (If it Fails It Stops) and its impact on the design, implementation and subsequent characteristics of circuits intended for application specific lC (ASIC) technology. The first study investigates the influences of information coding and protocol on the characteristics of IFIS systems. The second study investigates methods of circuit design applicable to IFIS cells and identifies the· technique possessing the characteristics most suitable for on-line testing. The third study investigates the characteristics of a 'real-life' commercial UART re-engineered using the techniques resulting from the previous two studies. The final study investigates the effects of the halting properties endowed by the protocol on failure diagnosis within IFIS systems. The outcome of this work is an identification and characterisation of the factors that influence behaviour, implementation costs and the ability to test and diagnose IFIS designs

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Achieving Functional Correctness in Large Interconnect Systems.

In today's semi-conductor industry, large chip-multiprocessors and systems-on-chip are being developed, integrating a large number of components on a single chip. The sheer size of these designs and the intricacy of the communication patterns they exhibit have propelled the development of network-on-chip (NoC) interconnects as the basis for the communication infrastructure in these systems. Faced with the interconnect's growing size and complexity, several challenges hinder its effective validation. During the interconnect's development, the functional verification process relies heavily on the use of emulation and post-silicon validation platforms. However, detecting and debugging errors on these platforms is a difficult endeavour due to the limited observability, and in turn the low verification capabilities, they provide. Additionally, with the inherent incompleteness of design-time validation efforts, the potential of design bugs escaping into the interconnect of a released product is also a concern, as these bugs can threaten the viability of the entire system. This dissertation provides solutions to enable the development of functionally correct interconnect designs. We first address the challenges encountered during design-time verification efforts, by providing two complementary mechanisms that allow emulation and post-silicon verification frameworks to capture a detailed overview of the functional behaviour of the interconnect. Our first solution re-purposes the contents of in-flight traffic to log debug data from the interconnect's execution. This approach enables the validation of the interconnect using synthetic traffic workloads, while attaining over 80% observability of the routes followed by packets and capturing valuable debugging information. We also develop an alternative mechanism that boosts observability by taking periodic snapshots of execution, thus extending the verification capabilities to run both synthetic traffic and real-application workloads. The collected snapshots enhance detection and debugging support, and they provide observability of over 50% of packets and reconstructs at least half of each of their routes. Moreover, we also develop error detection and recovery solutions to address the threat of design bugs escaping into the interconnect's runtime operation. Our runtime techniques can overcome communication errors without needing to store replicate copies of all in-flight packets, thereby achieving correctness at minimal area costsPhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116741/1/rawanak_1.pd

Design of fault-tolerant computers

Causes and symptoms of logic faults in digital systems. Reliable performance of hardware has been a require-ment for digital systems since the construction of the first digital computer. Improper functioning of the logic circuits in a digital system is manifested by logic faults, which are defined for this paper as "permanent or transient deviations of logic variables from the values specified in design." Permanent faults are caused by physical changes in the components of a logic circuit which permanently alter the logic function specified by the designer. The most common permanent faults are the determinate faults of "stuck on zero " and "stuck on one " types. Less frequent is the indeterminate or "stuck on X " fault