Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis

An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits

In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.Masdar Institute of Science and Technology (Massachusetts Institute of Technology Cooperative Agreement

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors

Article 09415

ABSTRACT INTRODUCTION Today's there square measure a growing range of moveable applications requiring small-area low-power highoutturn electronic equipment. Therefore, circuits with low power utilization grow to be the foremost vital candidates for style of microprocessors and system mechanism. The battery technology doesn't advance at constant rate because the electronics technology and there's a imperfect amount of power on the market for the mobile systems. The goal of extending the battery lifetime of moveable natural philosophy is to cut back the energy consumed per mathematical process, however low power consumption doesn't primarily imply low energy. To execute associate mathematical process, a circuit will acquire through low power by continuance at terribly low frequency however it's going to take a really lasting to complete the operation. Adder is a standout amongest the most fundamental segments of a CPU ( Central processing unit), Arithmetic logic unit (ALU), and coasting point unit and location era like store or memory access unit. Then again, expanding interest for versatile supplies Such as phones, personal digital assistant (PDA), and Notebook PC, emerge the need of utilizing zone and Power proficient VLSI circuits. Conventional adder is one in all the chief essential components of a processor that decides its out turn, and for address era just if there should be an occurrence of reserve or operation the complete adder execution would have an impact on the system as a whole. a spread of full adders. Abuse static or dynamic logic gates are accounted within the literature. In this paper, have a tendency to propose a logical methodology to style 10-transistor full adders and 28t full adders. Our new adders even have the limit misfortune issue; in any case, the adders square measure supportive in bigger circuits like multipliers regardless of the edge misfortune disadvantage. a substitution full adder known as static energy recovery full adder utilizes exclusively 10 transistors that has the most modest sum scope of transistors and has reduces the power dissipation, for every Power decline is one in all the first issues in today's VLSI style techniques as a consequence of a few reasons one is that the long battery in operation life interest of movable gadgets and second is owing to expanding scope of transistors on one chip brings about high power dissipation. The power consumption for CMOS circuits is described by the following equation: P avg = P dynamic + P short circuit + P leak Pavg =fclkCLαiV 2 dd + fclkI short V dd + I leak V dd Clearly see that the power depends on different parameters as well as on supply voltage (Vdd). Lowering Vdd would significantly reduce the power consumption of the circuit. This basic concept would be utilized to improve the power performance of the adder in this paper

Analysis and application of improved feedthrough logic

Continuous technology scaling and increased frequency of operation of VLSI circuits leads to increase in power density which raises thermal management problem. Therefore design of low power VLSI circuit technique is a challenging task without sacrificing its performance. This thesis presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough (FTL) logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The need for faster circuits compels designers to use FTL as compared static and domino CMOS logic and the requirement of output inverter for cascading of various logic blocks in domino logic are eliminated in the proposed design. The proposed circuit for low power (LP-FTL) improves dynamic power consumption as compared to the existing FTL and to further improve its speed we propose another circuit (HS-FTL). This logic family improves speed at the cost of dynamic power consumption and area. Proposed modified FTL circuit families provide better PDP as compared to the existing FTL. Simulation results of both the proposed circuit using 0.18 µm, 1.8 V CMOS process technology indicate that the LP-FTL structure reduces the dynamic power approximately by 42% and the HS-FTL structure achieves a speed up- 1.4 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing FTL logic. Furthermore, we present various circuit design techniques to improve noise tolerance of the proposed FTL logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (average noise threshold energy) metric is used for the analysis of noise tolerance of proposed FTL. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the nanometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity

Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits

The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations