A Spatial Sigma-Delta Approach to Mitigation of Power Amplifier Distortions in Massive MIMO Downlink

In massive multiple-input multiple-output (MIMO) downlink systems, the physical implementation of the base stations (BSs) requires the use of cheap and power-efficient power amplifiers (PAs) to avoid high hardware cost and high power consumption. However, such PAs usually have limited linear amplification ranges. Nonlinear distortions arising from operation beyond the linear amplification ranges can significantly degrade system performance. Existing approaches to handle the nonlinear distortions, such as digital predistortion (DPD), typically require accurate knowledge, or acquisition, of the PA transfer function. In this paper, we present a new concept for mitigation of the PA distortions. Assuming a uniform linear array (ULA) at the BS, the idea is to apply a Sigma-Delta ($\Sigma \Delta$) modulator to spatially shape the PA distortions to the high-angle region. By having the system operating in the low-angle region, the received signals are less affected by the PA distortions. To demonstrate the potential of this spatial $\Sigma \Delta$ approach, we study the application of our approach to the multi-user MIMO-orthogonal frequency division modulation (OFDM) downlink scenario. A symbol-level precoding (SLP) scheme and a zero-forcing (ZF) precoding scheme, with the new design requirement by the spatial $\Sigma \Delta$ approach being taken into account, are developed. Numerical simulations are performed to show the effectiveness of the developed $\Sigma \Delta$ precoding schemes

LOW PHASE NOISE CMOS PLL FREQUENCY SYNTHESIZER DESIGN AND ANALYSIS

The phase-locked loop (PLL) frequency synthesizer is a critical device of wireless transceivers. It works as a local oscillator (LO) for frequency translation and channel selection in the transceivers but suffers phase noise including reference spurs. In this dissertation for lowing phase noise and power consumption, efforts are placed on the new design of PLL components: VCOs, charge pumps and sigma delta modulators. Based on the analysis of the VCO phase noise generation mechanism and improving on the literature results, a design-oriented phase noise model for a complementary cross-coupled LC VCO is provided. The model reveals the relationship between the phase noise performance and circuit design parameters. Using this phase noise model, an optimized 2GHz low phase noise CMOS LC VCO is designed, simulated and fabricated. The theoretical analysis results are confirmed by the simulation and experimental results. With this VCO phase noise model, we also design a low phase noise, low gain wideband VCO with the typical VCO gain around 100MHz/V. Improving upon literature results, a complete quantitative analysis of reference spur is given in this dissertation. This leads to a design of a charge pump by using a negative feedback circuit and replica bias to reduce the current mismatch which causes the reference spur. In addition, low-impedance charge/discharge paths are provided to overcome the charge pump current glitches which also cause PLL spurs. With a large bit-width high order sigma delta modulator, the fractional-N PLL has fine frequency resolution and fast locking time. Based on an analysis of sigma delta modulator models introduced in this dissertation, a 3rd-order MASH 1-1-1 digital sigma delta modulator is designed. Pipelining techniques and true single phase clock (TSPC) techniques are used for saving power and area. Included is the design of a fully integrated 2.4GHz §¢ fractional-N CMOS PLL frequency synthesizer. It takes advantage of a sigma delta modulator to get a very fine frequency resolution and a relatively large loop bandwidth. This frequency synthesizer is a 4th-order charge pump PLL with 26MHz reference frequency. The loop bandwidth is about 150KHz, while the whole PLL phase noise is about -120dBc/Hz at 1MHz frequency offset

A Continuous-Time Delta-Sigma Modulator for Ultra-Low-Power Radios

The increasing need of digital signal processing for telecommunication and multimedia applications, implemented in complementary metal-oxide semiconductor (CMOS) technology, creates the necessity for high-resolution analog-to-digital converters (ADCs). Based on the sampling frequency, ADCs are of two types: Nyquist-rate converters and oversampling converters. Oversampling converters are preferred for low-bandwidth applications such as audio and instrumentation because they provide inherently high resolution when coupled with proper noise shaping. This allows to push noise out of signal band, thus increasing the signal-to-noise ratio (SNR). Continuous time delta-sigma ADCs are becoming more popular than discrete-time ADCs primarily because of inherent anti-aliasing filtering, reduced settling time and low-power consumption. In this thesis, a 2nd-order 4-bits continuous-time (CT) delta-sigma modulator (DSM) for radio applications is designed. It employs a 2nd-order loop filter with a single operational amplifier. Implemented in a 65-nanometer CMOS technology, the modulator runs on a 0.8-V supply and achieves a SNR of 70dB over a 500-kHz signal bandwidth. The modulator operates with an oversampling ratio (OSR) of 16 and a sampling frequency of 16MHz. In the first chapter the principles of ΔΣ modulators are analysed, introducing the differences between discrete-time (DT) modulators and continuous-time (CT) modulators. In the next chapter the techniques to design a ΔΣ modulators for ultra-low-power radios are presented. The third chapter talks over the design of the operational amplifier, which appears inside the loop filter. In the fourth chapter the performance of the complete ΔΣ modulator, which employs a flash quantizer, is shown. Finally, in the last chapter, a performance analysis is carried out replacing the flash quantizer with an asynchronous SAR quantizer. The analysis shows that a further reduction of the quantizer power consumption of about 40% is possible. The conjunction of this replacement with the power-saving technique implemented in the loop filter appears relevant

Design and implementation of a wideband sigma delta ADC

Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTƩ∆M), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications. The objective of this thesis is to design and implement a wideband CTƩ∆M for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTƩ∆M, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADC’s sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB. This thesis focuses on the design and implementation of the CTƩ∆M, building upon the principles of a discrete time Ʃ∆ modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTƩ∆ modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTƩ∆ modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTƩ∆M. The CTƩ∆Ms employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulator’s performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. Tiivistelmä. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistä tärkeämmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnän kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTƩ∆M), joissa käytetään ylinäytteistystä ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun. Tämän työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjärjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTƩ∆M, jolla on 15MHz:n signaalikaistanleveys. Ylinäytteistyssuhde on 25 ja AD muuntimen näytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR). Tämä työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Ʃ∆-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmä esitetään yksityiskohtaisesti, ja vaatimusten täyttyminen varmistetaan “top-down” -suunnitteluperiaatteella. Liitteenä on kertoimien laskemiseen käytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkän silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentä -DA muunninta. Viivekompensointipolkua käyttämällä modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. Lisäksi FIR takaisinkytkentä -DA-muuntimen käyttö pienentää kellojitteriherkkyyttä, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyä ja luotettavuutta. Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty peräkkäin integraattoreita myötäkytkentärakenteella (CIFF) ja toisessa sekä myötä- että takaisinkytkentärakenteella (CIFF-B). Päähuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa käyttäen 0.8 voltin käyttöjännitettä. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. Lisäksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin

Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters

Radar applications for driver assistance systems and autonomous vehicles have spurred the development of frequency-modulated continuous-wave (FMCW) radar. Continuous signal transmission and high operation frequencies in the K- and W-bands enable radar systems with low power consumption and small form factors. The radar performance depends on high-quality signal sources for chirp generation to ensure accurate and reliable target detection, requiring chirp synthesizers that offer fast frequency settling and low phase noise. Fractional-N phase locked loops (PLLs) are an effective tool for synthesis of FMCW waveform profiles, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Design approaches for FMCW chirp synthesizer PLLs need to address the conflicting requirements of fast settling and low close-in phase noise. While integrated PLLs can be implemented as analog or digital PLLs, analog PLLs still dominate for high frequencies. Digital PLLs offer greater programmability and area efficiency than their analog counterparts, but rely on high-resolution time-to-digital converters (TDCs) for low close-in phase noise. Performance limitations of conventional TDCs remain a roadblock for achieving low phase noise with high-frequency digital PLLs. This shortcoming of digital PLLs becomes even more pronounced with wide loop bandwidths as required for FMCW radar. To address this problem, this work presents digital FMCW chirp synthesizer PLLs using continuous-time delta-sigma TDCs. After a discussion of the requirements for PLL-based FMCW chirp synthesizers, this dissertation focuses on digital fractional-N PLL designs based on noise-shaping TDCs that leverage state-of-the-art delta-sigma modulator techniques to achieve low close-in phase noise in wide-bandwidth digital PLLs. First, an analysis of the PLL bandwidth and chirp linearity studies the design requirements for chirp synthesizer PLLs. Based on a model of a complete radar system, the analysis examines the impact of the PLL bandwidth on the radar performance. The modeling approach allows for a straightforward study of the radar accuracy and reliability as functions of the chirp parameters and the PLL configuration. Next, an 18-to-22GHz chirp synthesizer PLL that produces a 25-segment chirp for a 240GHz FMCW radar application is described. This synthesizer design adapts an existing third-order noise-shaping TDC design. A 65nm CMOS prototype achieves a measured close-in phase noise of -88dBc/Hz at 100kHz offset for wide PLL bandwidths and consumes 39.6mW. The prototype drives a radar testbed to demonstrate the effectiveness of the synthesizer design in a complete radar system. Finally, a second-order noise-shaping TDC based on a fourth-order bandpass delta-sigma modulator is introduced. This bandpass delta-sigma TDC leverages the high resolution of a bandpass delta-sigma modulator by sampling a sinusoidal PLL reference and applies digital down-conversion to achieve low TDC noise in the frequency band of interest. Based on the bandpass delta-sigma TDC, a 38GHz digital FMCW chirp synthesizer PLL is designed. The feedback divider applies phase interpolation with a phase rotation scheme to ensure the effectiveness of the low TDC noise. A prototype PLL, fabricated in 40nm CMOS, achieves a measured close-in phase noise of -85dBc/Hz at 100kHz offset for wide loop bandwidths >1MHz and consumes 68mW. It effectively generates fast (500MHz/55us) and precise (824kHz rms frequency error) triangular chirps for FMCW radar. The bandpass delta-sigma TDC achieves a measured integrated rms noise of 325fs in a 1MHz bandwidth.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147732/1/dweyer_1.pdfDescription of dweyer_1.pdf : Restricted to UM users only

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW