Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus physically continuous at all levels of inversion from linear operation to saturation. Hence, it lends itself conveniently for the use of a design methodology suited for low-power analog circuit design based on the inversion coefficient (IC) that has been extensively used in conjugation with the EIN model and allows to make simple calculations of, for example, transconductance efficiency, gain bandwidth product, etc. This methodology helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions. This paper will discuss the IC based design methodology and its application to the next generation BSIM6 compact MOSFET model. (C) 2013 Elsevier Ltd. All rights reserved

Double-gate MOSFET model implemented in VerilogAMS language for the transient simulation and the configuration of ultra low-power analog circuits

This paper deals with the implementation of a DCand AC double-gate MOSFET compact model in the VerilogAMS language for the transient simulation and the configurationof ultra low-power analog circuits. The Verilog-AMS descriptionof the proposed model is inserted in SMASH circuit simulator forthe transient simulation and the configuration of the Colpittsoscillator, the common-source amplifier, and the inverter. Theproposed model has the advantages of being simple and compact.It was validated using TCAD simulation results of the sametransistor realized with Silvaco Software

FOSS as an efficient tool for extraction of MOSFET compact model parameters

A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed

Modeling nanoscale quasi-ballistic MOS transistors:a circuit design perspective

The scaling of device technologies poses new challenges, not only in circuit design, but also in device modeling, especially because of the short-channel effects and the emergence of novel phenomena like ballistic transport. Nonetheless, it enables the design of ultra low-power analog and Radio Frequency (RF) circuits by allowing to push the operating points intomoderate and eventually weak inversion regions, which are increasingly becoming the preferred regions of operation for such applications. Even though modern compact models have evolved to adequately model the short-channel effects in all regions of operation, there is a lack of simpler models that (a) reliably predict the physics of downscaled devices while (b) remaining continuous through moderate inversion and (c) aid the designer’s intuition through simple designmethodologies. In this work, we extend the EKV charge based model to include the velocity saturation effect for weak inversion operation. Using the simple analytical model hence developed, we propose a design methodology for low-power analog circuit design. Then, we focus our attention on ballistic transport in MOSFETs, that is expected to dominate in the deeply scaled devices. Again, despite the extensive body of work available in the literature, most models remain deeply rooted in physics, consisting of fairly complicated equations, that are of little use for an intuitive understanding and design. In addition, the quasi-ballistic devices, which lie on the continuumbetween the ballistic and the diffusive devices, pose their own modeling challenges: a model for the quasi-ballistic devices would have to remain continuous between the ballistic and diffusive regimes. Most of the published works, based on the carrier flux transport over the source-channel potential barrier approach, seem to ignore the electrostatics in the rest of the channel. The shape of the electrostatic potential in the channel is approximated through polynomial functions, which is adequate for the very short-channel devices but not scalable to long channel quasi-ballistic devices. In this work, we study the role of the gate and the electrostatics in a ballistic channel by drawing on the insights gained from Monte-Carlo simulations on quasi-ballistic and ballistic doublegate MOSFETs. We propose a simple semi-empirical model of the channel charge, using which we develop an analytical model for the channel potential, both of which could be used as precursors to a scalable compact model that would encompass the ballistic, quasi-ballistic and drift-diffusion regimes

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Ultra-thin and flexible CMOS technology: ISFET-based microsystem for biomedical applications

A new paradigm of silicon technology is the ultra-thin chip (UTC) technology and the emerging applications. Very thin integrated circuits (ICs) with through-silicon vias (TSVs) will allow the stacking and interconnection of multiple dies in a compact format allowing a migration towards three-dimensional ICs (3D-ICs). Also, extremely thin and therefore mechanically bendable silicon chips in conjunction with the emerging thin-film and organic semiconductor technologies will enhance the performance and functionality of large-area flexible electronic systems. However, UTC technology requires special attention related to the circuit design, fabrication, dicing and handling of ultra-thin chips as they have different physical properties compared to their bulky counterparts. Also, transistors and other active devices on UTCs experiencing variable bending stresses will suffer from the piezoresistive effect of silicon substrate which results in a shift of their operating point and therefore, an additional aspect should be considered during circuit design. This thesis tries to address some of these challenges related to UTC technology by focusing initially on modelling of transistors on mechanically bendable Si-UTCs. The developed behavioural models are a combination of mathematical equations and extracted parameters from BSIM4 and BSIM6 modified by a set of equations describing the bending-induced stresses on silicon. The transistor models are written in Verilog-A and compiled in Cadence Virtuoso environment where they were simulated at different bending conditions. To complement this, the verification of these models through experimental results is also presented. Two chips were designed using a 180 nm CMOS technology. The first chip includes nMOS and pMOS transistors with fixed channel width and two different channel lengths and two different channel orientations (0° and 90°) with respect to the wafer crystal orientation. The second chip includes inverter logic gates with different transistor sizes and orientations, as in the previous chip. Both chips were thinned down to ∼20m using dicing-before-grinding (DBG) prior to electrical characterisation at different bending conditions. Furthermore, this thesis presents the first reported fully integrated CMOS-based ISFET microsystem on UTC technology. The design of the integrated CMOS-based ISFET chip with 512 integrated on-chip ISFET sensors along with their read-out and digitisation scheme is presented. The integrated circuits (ICs) are thinned down to ∼30m and the bulky, as well as thinned ICs, are electrically and electrochemically characterised. Also, the thesis presents the first reported mechanically bendable CMOS-based ISFET device demonstrating that mechanical deformation of the die can result in drift compensation through the exploitation of the piezoresistive nature of silicon. Finally, this thesis presents the studies towards the development of on-chip reference electrodes and biodegradable and ultra-thin biosensors for the detection of neurotransmitters such as dopamine and serotonin

Alterungsanalyse komplexer analoger integrierter Schaltungen aus Systemsicht

The design of analog circuits ranges from the specifications on system level, the selection of a suitable circuit topology up to the choice of the concrete physical dimensions of components like transistors. The individual steps are performed within computer-aided design environments. These environments are based on a database made available by the semiconductor manufacturers containing process parameters and influences on the components. In particular, the influences to be considered in the design have increased in recent years due to the continuous reduction of the producible structural sizes. Thus, it must be possible to analyze the deviations due to process, temperature, time degradation and, for special applications, radiation influences during the design phase. Conventional approaches regard these additional effects as standing next to the actual design process. As a result, the latter is no longer consistent and it is much more complex to consider different circuits and effects on different abstraction levels within the design flow. The focus of this work lies on the development of a consistent consideration of process, voltage, temperature, aging and radiation influences (PVTAR) during the entire design process of analog circuits to the initial measurement of manufactured circuits. To achieve this goal, a transistor model was extended by the influences to be considered. Thereby, the analysis of the additional effects is seamlessly integrated into conventional design processes and methods. In addition, the possibility of a structured analog design is evaluated. This approach allows the estimation of PVTAR influences on dedicated analog function blocks and their propagation on circuit level. Thus, the enormous simulation effort associated with aging analyses can be reduced. The design and manufacture of circuits is always followed by the measurement of the core properties of these circuits. In the context of this work a method was developed which makes it possible to use all insights from the design of a circuit for the improvement of the measuring results. In addition, the internal parameter sets of individual components can be inferred from the terminal behavior of circuits and systems. Finally, the results of the measurement method can be used for the automated calculation of circuit reliability parameters

Méthodologie de conception de circuits analogiques pour des applications radiofréquence à faible consommation de puissance

Thesis work are presented in the context of the integrated circuits design in advanced CMOS technology for ultra low power RF applications. The circuits are designed around two concepts. The first is the use of the inversion coefficient to normalize the transistor as a function of its size and its technology, this allows a quick analysis for different performances or different technologies. The second approach is to use a figure of merit to find the most appropriate polarization of a circuit based on its performance. These two principles were used to define effective design methods for two RF blocks: low noise amplifier and oscillator.Les travaux de thèse présentés se situent dans le contexte de la conception de circuits intégrés en technologie CMOS avancée pour des applications radiofréquence à très faible consommation de puissance. Les circuits sont conçus à travers deux concepts. Le premier est l'utilisation du coefficient d'inversion qui permet de normaliser le transistor en fonction de sa taille et de sa technologie, ceci permet une analyse rapide pour différentes performances visées ou différentes technologies. La deuxième approche est d'utiliser un facteur de mérite pour trouver la polarisation la plus adéquate d'un circuit en fonction de ses performances. Ces deux principes ont été utilisés pour définir des méthodes de conception efficaces pour deux blocs radiofréquence : l'amplificateur faible bruit et l'oscillateur