A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Full field image ranger hardware

We describe the hardware designed to implement a full field heterodyning imaging system. Comprising three key components - a light source, high speed shutter and a signal generator - the system is expected to be capable of simultaneous range measurements to millimetre precision over the entire field of view. Current modulated laser diodes provide the required illumination, with a bandwidth of 100 MHz and peak output power exceeding 600 mW. The high speed shutter action is performed by gating the cathode of an image intensifier, driven by a 50 Vpp waveform with 3.5 ns rise and fall times. A direct digital synthesiser, with multiple synchronised channels, provides high stability between its outputs, 160 MHz bandwidth and tuning of 0.1 Hz

A Smart Single-Chip Micro-Hotplate-Based Gas Sensor System in CMOS-Technology

This paper presents a monolithic chemical gas sensor system fabricated in industrial CMOS-technology combined with post-CMOS micromachining. The system comprises metal-oxide-covered (SnO2) micro-hotplates and the necessary driving and signal-conditioning circuitry. The SnO2 sensitive layer is operated at temperatures between 200 and 350°C. The on-chip temperature controller regulates the temperature of the membrane up to 350°C with a resolution of 0.5°C. A special heater-design was developed in order to achieve membrane temperatures up to 350°C with 5 V supply voltage. The heater design also ensures a homogeneous temperature distribution over the heated area of the hotplate (1-2% maximum temperature fluctuation). Temperature sensors, on- and off-membrane (near the circuitry), show an excellent thermal isolation between the heated membrane area and the circuitry-area on the bulk chip (chip temperature rises by max 6°C at 350°C membrane temperature). A logarithmic converter was included to measuring the SnO2 resistance variation upon gas exposure over a range of four orders of magnitude. An Analog Hardware Description Language (AHDL) model of the membrane was developed to enable the simulations of the complete microsystem. Gas tests evidenced a detection limit below 1 ppm for carbon monoxide and below 100 ppm for methan

Design of an Ultra-Low Power RTC for the IoT

The Internet of Things is growing at an exponential rate. This new perception of reality is being researched even further nowadays because society is starting to develop an interest on these technologies. Market potential is increasing even further, since the foreseeable implementations are diverse and still to be detected. The future applications for the IoT are enthusiastic and they will increase the overall quality of life of the citizens of the world. Developing a component that is crucial for the sustainability of this implementation is the task that truly motivates the intended work for this project. Designing the full-custom circuitry and physical layout of a Real Time Clock becomes a job that has a lot of minor details that need considerable attention. These technicalities truly tone the developers skill and knowledge of different design principles. Besides, developing the solution using subthreshold CMOS techniques will put emphasis on different technological procedures. Producing devices that are heavily dependent on PVT variations, operational frequency and power consumption define this new task, that needs a stable approach to all these diverse figure of merits, even though they are all interconnected. The study and understanding of these different approaches allows for a more complex in depth grasp of this recent intriguing proceedings