Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview

This paper presents a brief overview of past and current hardware acceleration (HwA) approaches that have been proposed for the most computationally intensive compression tools of the MPEG-4 standard. These approaches are classified based on their historical evolution and architectural approach. An analysis of both evolutionary and functional classifications is carried out in order to speculate on the possible trends of the HwA architectures to be employed in mobile video platforms

Efficient Architecture of Variable Size HEVC 2D-DCT for FPGA Platforms

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4×4, 8×8, 16×16, and 32×32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4K@30fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31-64% in hardware cost

Kemahiran boleh pindah dalam kalangan pelajar kejuruteraan di IPTA

Kemahiran boleh pindah didefinisikan sebagai kemahiran yang dimiliki oleh individu yang mempunyai kepelbagaian pengetahuan, nilai-nilai serta kemahiran hidup asas (life skills) yang diperlukan demi mendapatkan dan mengekalkan pekerjaan sedia ada. Kajian berbentuk tinjauan kuantitatif ini bertujuan untuk mengenal pasti persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya dari aspek adaptif, pemikiran kritis dan penyelesaian masalah. Di samping itu, kajian ini juga bertujuan untuk mengenal pasti perbezaan persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan perbezaan terhadap tahap penguasaannya di antara lelaki dan perempuan. Seramai 297 orang pelajar kejuruteraan tahun tiga lepasan matrikulasi Universiti Tun Hussein Onn Malaysia telah terpilih sebagai responden untuk menjawab borang soal selidik. Data dianalisis dengan mencari nilai skor min dan Ujian-t tidak bersandar menggunakan perisian Statistical Package for Social Science (SPSS). Dapatan kajian menunjukkan bahawa persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya berada pada tahap tinggi dengan nilai skor min 4.0864 dan 4.0282. Kajian juga menunjukkan bahawa wujudnya perbezaan yang signifikan dalam skor min persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah antara lelaki dan perempuan dengan nilai t signifikan 0.003. Namun begitu, hasil analisis menunjukkan tiada perbezaan bagi tahap penguasaannya dengan nilai t signifikan 0.327. Secara keseluruhannya, kesedaran yang tinggi akan membantu pelajar untuk menguasai keseluruhan kemahiran dengan sempurna. Ia juga boleh dijadikan panduan bagi pelajar untuk mengenal pasti elemen dan ciri-ciri yang diperlukan oleh majikan pada masa kini

Implementation of soft processor based SOC for JPEG compression on FPGA

With the advent of semiconductor process and EDA tools technology, IC designers can integrate more functions. However, to reduce the demand of time-to-market and tackle the increasing complexity of SoC, the need of fast prototyping and testing is growing. Taking advantage of deep submicron technology, modern FPGAs provide a fast and low-cost prototyping with large logic resources and high performance. So the hardware is mapped onto an emulation platform based on FPGA that mimics the behaviour of SOC. In this paper we use FPGA as a system on chip which is then used for image compression by 2-D DCT respectively and proposed SoC for image compression using soft core Microblaze. The JPEG standard defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. Proposed SoC for JPEG compression has been implemented on FPGA Spartan-6 SP605 evaluation board using Xilinx platform studio, because field programmable gate array have reconfigurable hardware architecture. Hence the JPEG image with high speed and reduced size can be obtained at low risk and low power consumption of about 0.699W. The proposed SoC for image compression is evaluated at 83.33MHz on Xilinx Spartan-6 FPGA

Kemahiran boleh pindah dalam kalangan pelajar kejuruteraan di IPTA

Kemahiran boleh pindah didefinisikan sebagai kemahiran yang dimiliki oleh individu yang mempunyai kepelbagaian pengetahuan, nilai-nilai serta kemahiran hidup asas (life skills) yang diperlukan demi mendapatkan dan mengekalkan pekerjaan sedia ada. Kajian berbentuk tinjauan kuantitatif ini bertujuan untuk mengenal pasti persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya dari aspek adaptif, pemikiran kritis dan penyelesaian masalah. Di samping itu, kajian ini juga bertujuan untuk mengenal pasti perbezaan persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan perbezaan terhadap tahap penguasaannya di antara lelaki dan perempuan. Seramai 297 orang pelajar kejuruteraan tahun tiga lepasan matrikulasi Universiti Tun Hussein Onn Malaysia telah terpilih sebagai responden untuk menjawab borang soal selidik. Data dianalisis dengan mencari nilai skor min dan Ujian-t tidak bersandar menggunakan perisian Statistical Package for Social Science (SPSS). Dapatan kajian menunjukkan bahawa persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya berada pada tahap tinggi dengan nilai skor min 4.0864 dan 4.0282. Kajian juga menunjukkan bahawa wujudnya perbezaan yang signifikan dalam skor min persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah antara lelaki dan perempuan dengan nilai t signifikan 0.003. Namun begitu, hasil analisis menunjukkan tiada perbezaan bagi tahap penguasaannya dengan nilai t signifikan 0.327. Secara keseluruhannya, kesedaran yang tinggi akan membantu pelajar untuk menguasai keseluruhan kemahiran dengan sempurna. Ia juga boleh dijadikan panduan bagi pelajar untuk mengenal pasti elemen dan ciri-ciri yang diperlukan oleh majikan pada masa kini

Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression

International audienceThe Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement

Energy efficient hardware acceleration of multimedia processing tools

The world of mobile devices is experiencing an ongoing trend of feature enhancement and generalpurpose multimedia platform convergence. This trend poses many grand challenges, the most pressing being their limited battery life as a consequence of delivering computationally demanding features. The envisaged mobile application features can be considered to be accelerated by a set of underpinning hardware blocks Based on the survey that this thesis presents on modem video compression standards and their associated enabling technologies, it is concluded that tight energy and throughput constraints can still be effectively tackled at algorithmic level in order to design re-usable optimised hardware acceleration cores. To prove these conclusions, the work m this thesis is focused on two of the basic enabling technologies that support mobile video applications, namely the Shape Adaptive Discrete Cosine Transform (SA-DCT) and its inverse, the SA-IDCT. The hardware architectures presented in this work have been designed with energy efficiency in mind. This goal is achieved by employing high level techniques such as redundant computation elimination, parallelism and low switching computation structures. Both architectures compare favourably against the relevant pnor art in the literature. The SA-DCT/IDCT technologies are instances of a more general computation - namely, both are Constant Matrix Multiplication (CMM) operations. Thus, this thesis also proposes an algorithm for the efficient hardware design of any general CMM-based enabling technology. The proposed algorithm leverages the effective solution search capability of genetic programming. A bonus feature of the proposed modelling approach is that it is further amenable to hardware acceleration. Another bonus feature is an early exit mechanism that achieves large search space reductions .Results show an improvement on state of the art algorithms with future potential for even greater savings

Low energy HEVC and VVC video compression hardware

Video compression standards compress a digital video by reducing and removing redundancy in the digital video using computationally complex algorithms. As spatial and temporal resolutions of videos increase, compression efficiencies of video compression algorithms are also increasing. However, increased compression efficiency comes with increased computational complexity. Therefore, it is necessary to reduce computational complexities of video compression algorithms without reducing their visual quality in order to reduce area and energy consumption of their hardware implementations. In this thesis, we propose a novel technique for reducing amount of computations performed by HEVC intra prediction algorithm. We designed low energy, reconfigurable HEVC intra prediction hardware using the proposed technique. We also designed a low energy FPGA implementation of HEVC intra prediction algorithm using the proposed technique and DSP blocks. We propose a reconfigurable VVC intra prediction hardware architecture. We also propose an efficient VVC intra prediction hardware architecture using DSP blocks. We designed low energy VVC fractional interpolation hardware. We propose a novel approximate absolute difference technique. We designed low energy approximate absolute difference hardware using the proposed technique. We propose a novel approximate constant multiplication technique. We designed approximate constant multiplication hardware using the proposed technique. We quantified computation reductions achieved by the proposed techniques and video quality loss caused by the proposed approximation techniques. The proposed approximate absolute difference technique and approximate constant multiplication technique cause very small PSNR loss. The other proposed techniques cause no PSNR loss. We implemented the proposed hardware architectures in Verilog HDL. We mapped the Verilog RTL codes to Xilinx Virtex 6 or Xilinx Virtex 7 FPGAs and estimated their power consumptions using Xilinx XPower Analyzer tool. The proposed techniques significantly reduced power and energy consumptions of these FPGA implementation