Spacecraft Data Handling Architecture based on AFDX network

International audienceThe Mission project (Methodology and assessment for the applicability of ARINC-664 (AFDX)[4] in Satellite/Spacecraft on-board communicatION networks), as an FP7 initiative for bringing terrestrial SME research into the space domain, aims to apply the Integrated Modular Avionics (IMA) concept on spacecraft, together with highly deterministic interconnected on-board network (ARINC-664, AFDX). It will constitute an enabling technology harmonization and standardization action. Together with an intrinsic improvement of systems performance, product assurance and reliability, it is expected to provide multiple benefits at all industrial level such as standardized and configurable systems, products and technology elements, easier and faster integration of complex systems, larger procurement basis, and easier subcontracting scheme. This paper presents the project objectives, architecture design, proof of concept demonstrator and current progress

Integration of Mission Control System, On-board Computer Core and spacecraft Simulator for a Satellite Test Bench: Integration of Mission Control System,On-board Computer Core and spacecraft Simulator for a Satellite Test Bench

The satellite avionics platform has been developed in cooperation with Airbus and is called „Future Low-cost Platform“ (FLP). It is based on an Onboard Computer (OBC) with redundant processor boards based on SPARC V8 microchips of type Cobham Aeroflex UT699. At the University of Stuttgart a test bench with a real hardware OBC and a fully simulated satellite is available for testing real flight scenarios with the Onboard Software (OBSW) running on representative hardware. The test bench as later the real flying satellite "Flying Laptop" – is commanded from a real Ground Control Centre (GCC). The main challenges in the FLP project were - Onboard computer design, - Software design and - Interfaces between platform and payloads In the course of industrialization of this FLP platform technology for later use in satellite constellations, Airbus has started to set up an in-house test bench where all the technologies shall be developed. The initial plan is to get first core elements of the FLP OBSW ported to the new dual-core processor and the new Space Wire(SpW) routing network. The plan also has an inclusion of new Mission Control Software with which one can command the OBC. The new OBC has a dual core processor Cobham Gaisler GR712 and hence, all the payload and related functionality are to be implemented only in a second core which involves a lot of low-level task distribution. The consequent SpW router network application and dual-core platform/payload OBSW sharing are entirely new in the field of satellite engineering

SHINe: Simulator for satellite on-board high-speed networks featuring SpaceFibre and SpaceWire protocols

The continuous innovation of satellite payloads is leading to an increasing demand of data-rate for on-board satellite networks. In particular, modern optical detectors generate and need to transfer data at more than 1 Gbps, a speed that cannot be satisfied with standardized technologies such as SpaceWire. To fill this gap, the European Space Agency (ESA) is supporting the development of a new high-speed link standard, SpaceFibre. SpaceFibre provides a data-rate higher than 6.25 Gbps, together with the possibility to use multiple Virtual Channels running over the same physical link, each one configurable with flexible Quality of Service parameters. These features make a SpaceFibre network very appealing but also complex to set up in order to achieve the desired end-to-end requirements. To help this process, a Simulator for HIgh-speed Network (SHINe) based on the open-source toolkit OMNeT++ has been developed and is presented in this paper. It supports the simulation of SpaceFibre and SpaceWire protocols in order to help both the final steps of the standardization process and the system engineers in the setup and test of new networks. SHINe allows to precisely simulate common network metrics, such as latency and bandwidth usage, and it can be connected to real hardware in a Hardware-in-the-Loop configuration

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans

Universal Reconfigurable Translator Module (URTM) Final Report

This report describes the Universal Reconfigurable Translation Module, or URTM. The URTM was developed by Sigma Space Corporation for NASA in order to translate specific serial protocols, both logically and physically. At present, the prototype configuration has targeted MIL-STD-1553B (RT and BC), IEEE 1394b (Firewire), and ECSS-E-50-12A (SpaceWire). The objectives of this program were to study the feasibility of a configurable URTM to translate serial link data as might be used in a space-flight mission and to design, develop, document, and deliver an engineering prototype model of the URTM with a path to spaceflight. By simply connecting two of the three Physical Interface Modules (PIM) on either end of the RPTM (Reconfigurable Protocol Translator Module), the URTM then self configures via a library of interface translation functions, thereby allowing the two data links to communicate seamlessly

Analyse und Erweiterung eines fehler-toleranten NoC für SRAM-basierte FPGAs in Weltraumapplikationen

Data Processing Units for scientific space mission need to process ever higher volumes of data and perform ever complex calculations. But the performance of available space-qualified general purpose processors is just in the lower three digit megahertz range, which is already insufficient for some applications. As an alternative, suitable processing steps can be implemented in hardware on a space-qualified SRAM-based FPGA. However, suitable devices are susceptible against space radiation. At the Institute for Communication and Network Engineering a fault-tolerant, network-based communication architecture was developed, which enables the construction of processing chains on the basis of different processing modules within suitable SRAM-based FPGAs and allows the exchange of single processing modules during runtime, too. The communication architecture and its protocol shall isolate non SEU mitigated or just partial SEU mitigated modules affected by radiation-induced faults to prohibit the propagation of errors within the remaining System-on-Chip. In the context of an ESA study, this communication architecture was extended with further components and implemented in a representative hardware platform. Based on the acquired experiences during the study, this work analyses the actual fault-tolerance characteristics as well as weak points of this initial implementation. At appropriate locations, the communication architecture was extended with mechanisms for fault-detection and fault-differentiation as well as with a hardware-based monitoring solution. Both, the former measures and the extension of the employed hardware-platform with selective fault-injection capabilities for the emulation of radiation-induced faults within critical areas of a non SEU mitigated processing module, are used to evaluate the effects of radiation-induced faults within the communication architecture. By means of the gathered results, further measures to increase fast detection and isolation of faulty nodes are developed, selectively implemented and verified. In particular, the ability of the communication architecture to isolate network nodes without SEU mitigation could be significantly improved.Instrumentenrechner für wissenschaftliche Weltraummissionen müssen ein immer höheres Datenvolumen verarbeiten und immer komplexere Berechnungen ausführen. Die Performanz von verfügbaren qualifizierten Universalprozessoren liegt aber lediglich im unteren dreistelligen Megahertz-Bereich, was für einige Anwendungen bereits nicht mehr ausreicht. Als Alternative bietet sich die Implementierung von entsprechend geeigneten Datenverarbeitungsschritten in Hardware auf einem qualifizierten SRAM-basierten FPGA an. Geeignete Bausteine sind jedoch empfindlich gegenüber der Strahlungsumgebung im Weltraum. Am Institut für Datentechnik und Kommunikationsnetze wurde eine fehlertolerante netzwerk-basierte Kommunikationsarchitektur entwickelt, die innerhalb eines geeigneten SRAM-basierten FPGAs Datenverarbeitungsmodule miteinander nach Bedarf zu Verarbeitungsketten verbindet, sowie den Austausch von einzelnen Modulen im Betrieb ermöglicht. Nicht oder nur partiell SEU mitigierte Module sollen bei strahlungsbedingten Fehlern im Modul durch das Protokoll und die Fehlererkennungsmechanismen der Kommunikationsarchitektur isoliert werden, um ein Ausbreiten des Fehlers im restlichen System-on-Chip zu verhindern. Im Kontext einer ESA Studie wurde diese Kommunikationsarchitektur um Komponenten erweitert und auf einer repräsentativen Hardwareplattform umgesetzt. Basierend auf den gesammelten Erfahrungen aus der Studie, wird in dieser Arbeit eine Analyse der tatsächlichen Fehlertoleranz-Eigenschaften sowie der Schwachstellen dieser ursprünglichen Implementierung durchgeführt. Die Kommunikationsarchitektur wurde an geeigneten Stellen um Fehlerdetektierungs- und Fehlerunterscheidungsmöglichkeiten erweitert, sowie um eine hardwarebasierte Überwachung ergänzt. Sowohl diese Maßnahmen, als auch die Erweiterung der Hardwareplattform um gezielte Fehlerinjektions-Möglichkeiten zum Emulieren von strahlungsinduzierten Fehlern in kritischen Komponenten eines nicht SEU mitigierten Prozessierungsmoduls werden genutzt, um die tatsächlichen auftretenden Effekte in der Kommunikationsarchitektur zu evaluieren. Anhand der Ergebnisse werden weitere Verbesserungsmaßnahmen speziell zur schnellen Detektierung und Isolation von fehlerhaften Knoten erarbeitet, selektiv implementiert und verifiziert. Insbesondere die Fähigkeit, fehlerhafte, nicht SEU mitigierte Netzwerkknoten innerhalb der Kommunikationsarchitektur zu isolieren, konnte dabei deutlich verbessert werden

SatCat5: A Low-Power, Mixed-Media Ethernet Network for Smallsats

In any satellite, internal bus and payload systems must exchange a variety of command, control, telemetry, and mission-data. In too many cases, the resulting network is an ad-hoc proliferation of complex, dissimilar protocols with incomplete system-to-system connectivity. While standards like CAN, MIL-STD-1553, and SpaceWire mitigate this problem, none can simultaneously solve the need for high throughput and low power consumption. We present a new solution that uses Ethernet framing and addressing to unify a mixed-media network. Low-speed nodes (0.1-10 Mbps) use simple interfaces such as SPI and UART to communicate with extremely low power and minimal complexity. High-speed nodes use so-called “media-independent” interfaces such as RMII, RGMII, and SGMII to communicate at rates up to 1000 Mbps and enable connection to traditional COTS network equipment. All are interconnected into a single smallsat-area-network using a Layer-2 network switch, with mixed-media support for all these interfaces on a single network. The result is fast, easy, and flexible communication between any two subsystems. SatCat5 is presented as a free and open-source reference implementation of this mixed-media network switch, with power consumption of 0.2-0.7W depending on network activity. Further discussion includes example protocols that can be used on such networks, leveraging IPv4 when suitable but also enabling full-featured communication without the need for a complex protocol stack

PROPOSED MIDDLEWARE SOLUTION FOR RESOURCE-CONSTRAINED DISTRIBUTED EMBEDDED NETWORKS

The explosion in processing power of embedded systems has enabled distributed embedded networks to perform more complicated tasks. Middleware are sets of encapsulations of common and network/operating system-specific functionality into generic, reusable frameworks to manage such distributed networks. This thesis will survey and categorize popular middleware implementations into three adapted layers: host-infrastructure, distribution, and common services. This thesis will then apply a quantitative approach to grading and proposing a single middleware solution from all layers for two target platforms: CubeSats and autonomous unmanned aerial vehicles (UAVs). CubeSats are 10x10x10cm nanosatellites that are popular university-level space missions, and impose power and volume constraints. Autonomous UAVs are similarly-popular hobbyist-level vehicles that exhibit similar power and volume constraints. The MAVLink middleware from the host-infrastructure layer is proposed as the middleware to manage the distributed embedded networks powering these platforms in future projects. Finally, this thesis presents a performance analysis on MAVLink managing the ARM Cortex-M 32-bit processors that power the target platforms