Power Droop Reduction In Logic BIST By Scan Chain Reordering

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

Reduction of perceptual redundancy for data compression of television signals

Imperial Users onl

Study to investigate and evaluate means of optimizing the Ku-band combined radar/communication functions for the space shuttle

The performance of the space shuttle orbiter's Ku-Band integrated radar and communications equipment is analyzed for the radar mode of operation. The block diagram of the rendezvous radar subsystem is described. Power budgets for passive target detection are calculated, based on the estimated values of system losses. Requirements for processing of radar signals in the search and track modes are examined. Time multiplexed, single-channel, angle tracking of passive scintillating targets is analyzed. Radar performance in the presence of main lobe ground clutter is considered and candidate techniques for clutter suppression are discussed. Principal system parameter drivers are examined for the case of stationkeeping at ranges comparable to target dimension. Candidate ranging waveforms for short range operation are analyzed and compared. The logarithmic error discriminant utilized for range, range rate and angle tracking is formulated and applied to the quantitative analysis of radar subsystem tracking loops

A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.Ph.D.Committee Chair: Kim, Jongman; Committee Member: Kang, Sung Ha; Committee Member: Lee, Chang-Ho; Committee Member: Mukhopadhyay, Saibal; Committee Member: Tentzeris, Emmanouil

An Image Enhancement Approach to Achieve High Speed Using Adaptive Modified Bilateral Filter for Satellite Images Using FPGA

For real time application scenarios of image processing, satellite imaginary has grown more interest by researches due to the informative nature of image. Satellite images are captured using high quality cameras. These images are captured from space using on-board cameras. Wrong ISO setting, camera vibrations or wrong sensory setting causes noise. The degraded image can cause less efficient results during visual perception which is a challenging issue for researchers. Another reason is that noise corrupts the image during acquisition, transmission, interference or dust particles on the scanner screen of image from satellite to the earth stations. If quality degraded images are used for further processing then it may result in wrong information extraction. In order to cater this issue, image filtering or denoising approach is required. Since remote sensing images are captured from space using on-board camera which requires high speed operating device which can provide better reconstruction quality by utilizing lesser power consumption. Recently various approaches have been proposed for image filtering. Key challenges with these approaches are reconstruction quality, operating speed, image quality by preserving information at edges on image. Proposed approach is named as modified bilateral filter. In this approach bilateral filter and kernel schemes are combined. In order to overcome the drawbacks, modified bilateral filtering by using FPGA to perform the parallelism process for denoising is implemented

Protecting the Future Grid: An Electric Vehicle Robust Mitigation Scheme Against Load Altering Attacks on Power Grids

Due to the growing threat of climate change, the worlds governments have been encouraging the adoption of Electric Vehicles (EVs). As a result, EV numbers have been growing exponentially which will introduce a large EV charging load into the power grid. On this basis, we present a scheme to utilize EVs as a defense mechanism to mitigate Load-Altering (LA) attacks against the grid. The developed scheme relies on robust control theory and Linear Matrix Inequalities (LMIs). Our EV-based defense mechanism is formulated as a feedback controller synthesized using H-2 and H-infinity control techniques to eliminate the impact of unknown LA attacks. The controller synthesis considers the grid topology and the uncertainties of the EV connection to the grid. To demonstrate the effectiveness of the proposed mitigation scheme, it is tested against three types of LA attacks on the New England 39-bus grid. We test our mitigation scheme against 800 MW static, switching, and dynamic attacks in the presence of multiple sources of uncertainty that can affect the EV load during deployment. The results demonstrate how the grid remains stable under the LA attacks that would otherwise lead to serious instabilities.Comment: Accepted for publication in Applied Energ

Noise source identification on large generator units

Abstract unavailable please refer to PD