Analog-to-digital interface design in wireless receivers

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

Low power encoder and comparator design of 5-bit flash ADC

The present work of the thesis is divided into two parts, first is design of a low power encoder and second is low power latched comparator design. In this low power encoding scheme proposed for 4GS/s 5 bit flash analog to digital converter. The demanding issues in the design of a low power flash ADC is the design of thermometer code to binary code. An encoder in this thesis converts the thermo-meter code into binary code without any intermediate stage using dynamic CMOS logic. To decrease the power consumption of the Flash ADC, the implementation of encoder and comparator is done using dynamic CMOS logic. The proposed encoder in this thesis is designed using 90nm technology at 1.2V DC voltage source using CADENCE tool. The simulation results of 5-bit Flash ADC block is shown for a sampling frequency up to 4GHz and at 4GHz the encoder circuit showing the average power dissipation of the encoder block is 1.833 µW.The other part of the present work is the design of low power comparator for the 5-bit flash ADC. Dynamic latch comparator has been designed in order to reduce power dissipation, delays etc. The different parts of the dynamic latch comparator like: pre-amplifier, dynamic latch, and output buffer are implemented on CADENCE tool with 1.2 V power supply. The simulation results shown for a sampling frequency of 5 GHz and the average power dissipation of the proposed comparator is 69.09 µW. The physical layout of the encoder and comparator has been drawn using CADENCE VIRTUSO LAYOUT EDITOR. The DRC errors has been removed and the layout has been matched with the schematics

A Low Power Mid-Rail Dual Slope Analog-To-Digital Converter for Biomedical Instrumentation

There are an estimated 15 million babies born preterm every year and it is on the rise. The complications that arise from this can be quite severe and are the leading causes of death among children under 5 years of age. Among these complications is a condition known as apnea. This disorder is defined as the suspension of breathing during sleep for usually 10 to 30 seconds and can occur up to 20-30 times per hour for preterm infants. This lack of oxygen in the bloodstream can have troubling effects, such as brain damage and death if the apnea period is longer than expected. This creates a dire need to continuously monitor the respiration state of babies born prematurely. Given that the breathing signal is in analog form, a conversion to its digital counterpart is necessary.In this thesis, a novel low power analog-to-digital converter (ADC) for the digitization and analyzation of the respiration signal is presented. The design of the ADC demonstrates an innovative approach on how to operate on a single polarity supply system, which effectively doubles the sampling speed. The ADC has been realized in a standard 130 nm CMOS process

Design of high speed folding and interpolating analog-to-digital converter

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate

Reporte de formación complementaria en área de concentración en diseño de circuitos integrados analógicos

Los proyectos realizados y que se describen aquí son: Diseño Físico de Circuitos Integrados (Etapa de 1.5 bits de un convertidor A/D tipo Pipeline); Diseño de Circuitos Integrados Analógicos (Design of a Programmable Charge-Pump Waveform Generator); Diseño Avanzado de Circuitos Integrados (diseño de un filtro activo pasa bajas elíptico de 5º orden); Tópicos Avanzados en Diseño de Circuitos Integrados Analógicos (diseño de un convertidor A/D de 5 bits con arquitectura de registro de aproximaciones-sucesivas)

Digitally Assisted ADCS.

This work involves the development of digital calibration techniques for Analogto- Digital Converters. According to the 2001 International Technology Roadmap for Semiconductors, improved ADC technology is a key factor in the development of present and future applications. The switched-capacitor (SC) pipeline technique is the most popular method of implementing moderate resolution ADCs. However the advantages of CMOS, which originally made SC circuits feasible, are being eroding by process scaling. Good switches and opamps are becoming increasingly difficult to design and the growing gate leakage of deep submicron MOSFETs is causing difficulty. Traditional ADC schemes do not work well with supply voltages of 1.8V and below. Furthermore, the performance required by present and future wireless and IT applications will not be met by the present day ADC circuits techniques. Bearing in mind the challenges associated with deep sub-micron analog circuitry a new calibration technique for folding ADCs has been developed. Since digital circuitry scales well, this calibration relies heavily on digital techniques. Hence it reduces the amount of analog design involved. As this folding ADC is dominated, in terms of both functionality and power, by digital circuitry, the performance of folding will improve when implemented in smaller geometry processes. An 8-bit, 500MS/s, digitally calibrated folding ADC was designed in TSMC 0.18mm. A second prototype, 9-bit 400MS/s, was designed in ST 90nm. This ADC uses novel folders to reduce thermal noise. The major accomplishments of this work are: · The creation of a new folding ADC architecture that is digitally dominated allowing large transistor mismatch to be tolerated so that small devices can be utilized in the signal path. · The development of modeling techniques, to investigate and analyze the effects of transistor mismatch, folder linearity and redundancy in ADCs. · The design of a new folder circuit topology that decreases the required power consumption for a given noise budget. · The design of a resistor ladder DAC that uses a unique resistor layout to allow any shape ladder to be designed.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58426/1/ibogue_1.pd

Third order CMOS decimator design for sigma delta modulators

A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed

Low-power current-mode ADC for CMOS sensor IC

A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate with very low duty cycle due to limited energy. Ideally these sensor networks will be massive in size and dense in order to promote redundancy. In addition the networks will be collectively intelligent and adaptive. To achieve these goals, distributed sensor networks will require very small,inexpensive nodes that run for long periods of time on very little energy. One component of such network nodes is an A/D converter. An ADC acts as a crucial interface between the sensed environment and the sensor network as a whole. The work presented here focuses on moderate resolution, and moderate speed, but ultra-low-power ADCs. The 6 bit current-mode algorithmic pipelined ADC reported here consumes 8 pJ/bit samples at 0.65V supply and 130 kS/s. The current was chosen as the information carrying quantity instead of voltage as it is more favorable for low-voltage and low-power applications. The reference current chosen was 150nA. All the blocks are using transistors operating in subthreshold or weak inversion region of operation, to work in low-voltage and low current supply. The DNL and INL plots are given in simulation results section. The area of the overall ADC was 0.046 mm2 only