Análise Experimental da conversão RGB/YCbCr e codificação Run-length para compressão de imagens em Sistemas de Tempo Real Baseados em VANTs / Experimental Analysis of RGB/YCbCr conversion and Run-length encoding for image compression in UAV-based Real-Time Systems

Atualmente muitas aplicações que fazem uso de  VANT’s  capturam imagens RGB e as enviam para uma base em terra, em tempo real. O tamanho da imagem transferida é fundamental no atendimento dos requisitos temporais da aplicação Run-length (RLE) e´ uma técnica de compressão de dados adequada para longas sequências de repetições. Foi realizada a conversão RGB/YCbCr e executado o algoritmo de compactação RLE em cada um desses dois espaços de cores.  Os resultados obtidos neste estudo experimental, indicam que a técnica run-length, aplicada ao sistema de cores YCbCr, apresenta vantagens em relação ao RGB, tanto em tempo de processamento quanto em relação as taxas de redução

Metodologia de Reconfiguração de Hardware utilizando o Sinal de TV Digital

O presente artigo apresenta um modelo de Set-top Box (STB) com decodificador de vídeo reconfigurável, funcionando a partir do sinal aberto de TV Digital (TVD). O modelo foi baseado em uma plataforma comercial e utiliza um módulo de Field Programmable Gate Array (FPGA) para o processo de reconfiguração, no qual é prevista a atualização do decodificador de vídeo H.264. O sistema efetua a reconfiguração do FPGA a partir de um feixe de bits contendo a descrição de hardware (H.264), o qual é  transmitido juntamente com o conteúdo de TV em alta definição (High Definition Television --  HDTV). Dessa maneira, todos os receptores na área de cobertura da transmissora de TVD podem ser atualizados através de um único sinal. A transmissão e a recepção dos dados de atualização fazem parte do modelo conceitual proposto, cujo desenvolvimento objetiva  a minimização do legado normalmente existente na implantação ou na evolução de um sistema de TVD. Assim, futuras revisões nas normas de TVD poderiam ocorrer sem a necessidade de troca de equipamento

Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications

Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications

Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications