Hybrid monolithic integration of high-power DC-DC converters in a high-voltage technology

The supply of electrical energy to home, commercial, and industrial users has become ubiquitous, and it is hard to imagine a world without the facilities provided by electrical energy. Despite the ever increasing efficiency of nearly every electrical application, the worldwide demand for electrical power continues to increase, since the number of users and applications more than compensates for these technological improvements. In order to maintain the affordability and feasibility of the total production, it is essential for the distribution of the produced electrical energy to be as efficient as possible. In other words the loss in the power distribution is to be minimized. By transporting electrical energy at the maximum safe voltage, the current in the conductors, and the associated conduction loss can remain as low as possible. In order to optimize the total efficiency, the high transportation voltage needs to be converted to the appropriate lower voltage as close as possible to the end user. Obviously, this conversion also needs to be as efficient, affordable, and compact as possible. Because of the ever increasing integration of electronic systems, where more and more functionality is combined in monolithically integrated circuits, the cost, the power consumption, and the size of these electronic systems can be greatly reduced. This thorough integration is not limited to the electronic systems that are the end users of the electrical energy, but can also be applied to the power conversion itself. In most modern applications, the voltage conversion is implemented as a switching DC-DC converter, in which electrical energy is temporarily stored in reactive elements, i.e. inductors or capacitors. High switching speeds are used to allow for a compact and efficient implementation. For low power levels, typically below 1 Watt, it is possible to monolithically implement the voltage conversion on an integrated circuit. In some cases, this is even done on the same integrated circuit that is the end user of the electrical energy to minimize the system dimensions. For higher power levels, it is no longer feasible to achieve the desired efficiency with monolithically integrated components, and some external components prove indispensable. Usually, the reactive components are the main limiting factor, and are the first components to be moved away from the integrated circuit for increasing power levels. The semiconductor components, including the power transistors, remain part of the integrated circuit. Using this hybrid approach, it is possible in modern converterapplications to process around 60 Watt, albeit limited to voltages of a few Volt. For hybrid integrated converters with an output voltage of tens of Volt, the power is limited to approximately 10 Watt. For even higher power levels, the integrated power transistors also become a limiting factor, and are replaced with discrete power devices. In these discrete converters, greatly increased power levels become possible, although the system size rapidly increases. In this work, the limits of the hybrid approach are explored when using so-called smart-power technologies. Smart-power technologies are standard lowcost submicron CMOS technologies that are complemented with a number of integrated high-voltage devices. By using an appropriate combination of smart-power technologies and circuit topologies, it is possible to improve on the current state-of-the-art converters, by optimizing the size, the cost, and the efficiency. To determine the limits of smart-power DC-DC converters, we first discuss the major contributing factors for an efficient energy distribution, and take a look at the role of voltage conversion in the energy distribution. Considering the limitations of the technologies and the potential application areas, we define two test-cases in the telecommunications sector for which we want to optimize the hybrid monolithic integration in a smart-power technology. Subsequently, we explore the specifications of an ideal converter, and the relevant properties of the affordable smart-power technologies for the implementation of DC-DC converters. Taking into account the limitations of these technologies, we define a cost function that allows to systematically evaluate the different potential converter topologies, without having to perform a full design cycle for each topology. From this cost function, we notice that the de facto default topology selection in discrete converters, which is typically based on output power, is not optimal for converters with integrated power transistors. Based on the cost function and the boundary conditions of our test-cases, we determine the optimal topology for a smart-power implementation of these applications. Then, we take another step towards the real world and evaluate the influence of parasitic elements in a smart-power implementation of switching converters. It is noticed that the voltage overshoot caused by the transformer secondary side leakage inductance is a major roadblock for an efficient implementation. Since the usual approach to this voltage overshoot in discrete converters is not applicable in smart-power converters due to technological limitations, an alternative approach is shown and implemented. The energy from the voltage overshoot is absorbed and transferred to the output of the converter. This allows for a significant reduction in the voltage overshoot, while maintaining a high efficiency, leading to an efficient, compact, and low-cost implementation. The effectiveness of this approach was tested and demonstrated in both a version using a commercially available integrated circuit, and our own implementation in a smart-power integrated circuit. Finally, we also take a look at the optimization of switching converters over the load range by exploiting the capabilities of highly integrated converters. Although the maximum output power remains one of the defining characteristics of converters, it has been shown that most converters spend a majority of their lifetime delivering significantly lower output power. Therefore, it is also desirable to optimize the efficiency of the converter at reduced output current and output power. By splitting the power transistors in multiple independent segments, which are turned on or off in function of the current, the efficiency at low currents can be significantly improved, without introducing undesirable frequency components in the output voltage, and without harming the efficiency at higher currents. These properties allow a near universal application of the optimization technique in hybrid monolithic DC-DC converter applications, without significant impact on the complexity and the cost of the system. This approach for the optimization of switching converters over the load range was demonstrated using a boost converter with discrete power transistors. The demonstration of our smart-power implementation was limited to simulations due to an issue with a digital control block. On a finishing note, we formulate the general conclusions and provide an outlook on potential future work based on this research

The 10 to the 8th power bit solid state spacecraft data recorder

The results are summarized of a program to demonstrate the feasibility of Bubble Domain Memory Technology as a mass memory medium for spacecraft applications. The design, fabrication and test of a partially populated 10 to the 8th power Bit Data Recorder using 100 Kbit serial bubble memory chips is described. Design tradeoffs, design approach and performance are discussed. This effort resulted in a 10 to the 8th power bit recorder with a volume of 858.6 cu in and a weight of 47.2 pounds. The recorder is plug reconfigurable, having the capability of operating as one, two or four independent serial channel recorders or as a single sixteen bit byte parallel input recorder. Data rates up to 1.2 Mb/s in a serial mode and 2.4 Mb/s in a parallel mode may be supported. Fabrication and test of the recorder demonstrated the basic feasibility of Bubble Domain Memory technology for such applications. Test results indicate the need for improvement in memory element operating temperature range and detector performance

Hard macrocells for DC/DC converter in automotive embedded mechatronic systems

A novel configurable DC/DC converter architecture, to be integrated as hard macrocell in automotive embedded systems, is proposed in the paper. It aims at realizing an intelligent voltage regulator. With respect to the state of the art, the challenge is the integration into an automotive-qualified chip of several advanced features like dithering of switching frequency, nested control loops with both current and voltage feedback, asynchronous hysteretic control for low power mode, slope control of the power FET gate driver, and diagnostic block against out-of-range current or voltage or temperature conditions. Moreover, the converter macrocell can be connected to the in-vehicle digital network, exchanging with the main vehicle control unit status/diagnostic flags and commands. The proposed design can be configured to work both in step-up and step-down modes, to face a very wide operating input voltage range from 2.5 to 60 V and absolute range from −0.3 to 70 V. The main target is regulating all voltages required in the emerging hybrid/electric vehicles where, besides the conventional 12 V DC bus, also a 48 V DC bus is present. The proposed design supports also digital configurability of the output regulated voltage, through a programmable divider, and of the coefficients of the proportional-integrative controller inside the nested control loops. Fabricated in 0.35 μm CMOS technology, experimental measurements prove that the IC can operate in harsh automotive environments since it meets stringent requirements in terms of electrostatic discharge (ESD) protection, operating temperature range, out-of-range current, or voltage condition

Recent Advances in Neural Recording Microsystems

The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field

DEVELOPMENT OF A SIMPLIFIED, MASS PRODUCIBLE HYBRIDIZED AMBIENT, LOW FREQUENCY, LOW INTENSITY VIBRATION ENERGY SCAVENGER (HALF-LIVES)

Scavenging energy from environmental sources is an active area of research to enable remote sensing and microsystems applications. Furthermore, as energy demands soar, there is a significant need to explore new sources and curb waste. Vibration energy scavenging is one environmental source for remote applications and a candidate for recouping energy wasted by mechanical sources that can be harnessed to monitor and optimize operation of critical infrastructure (e.g. Smart Grid). Current vibration scavengers are limited by volume and ancillary requirements for operation such as control circuitry overhead and battery sources. This dissertation, for the first time, reports a mass producible hybrid energy scavenger system that employs both piezoelectric and electrostatic transduction on a common MEMS device. The piezoelectric component provides an inherent feedback signal and pre-charge source that enables electrostatic scavenging operation while the electrostatic device provides the proof mass that enables low frequency operation. The piezoelectric beam forms the spring of the resonant mass-spring transducer for converting vibration excitation into an AC electrical output. A serially poled, composite shim, piezoelectric bimorph produces the highest output rectified voltage of over 3.3V and power output of 145uW using ¼ g vibration acceleration at 120Hz. Considering solely the volume of the piezoelectric beam and tungsten proof mass, the volume is 0.054cm3, resulting in a power density of 2.68mW/cm3. Incorporation of a simple parallel plate structure that provides the proof mass for low frequency resonant operation in addition to cogeneration via electrostatic energy scavenging provides a 19.82 to 35.29 percent increase in voltage beyond the piezoelectric generated DC rails. This corresponds to approximately 2.1nW additional power from the electrostatic scavenger component and demonstrates the first instance of hybrid energy scavenging using both piezoelectric and synchronous electrostatic transduction. Furthermore, it provides a complete system architecture and development platform for additional enhancements that will enable in excess of 100uW additional power from the electrostatic scavenger

Design and Simulation of a DC Electric Vehicle Charging Station Interconnected with a MVDC Network

Due to a rapidly aging electric transmission and distribution infrastructure, an increased demand for energy, an increased awareness of climate change and greenhouse gas pollution, and an increased cost of fuel there is a need to produce and deliver energy more efficiently. This thesis attempts to provide a solution to these constraints through advancements in DC power architectures. Medium Voltage Direct Current (MVDC) infrastructure serves as a platform for the interconnection of renewable electric power generation, including wind and solar. Abundant loads such as industrial facilities, data centers, commercial office buildings, industrial parks, and electric vehicle charging stations (EVCS) can also be powered using MVDC technology. MVDC networks are expected to improve efficiency, through reductions in power electronic conversion steps and by serving as an additional layer between the transmission and distribution level voltage for which generation sources and loads could directly interface with smaller rated power conversion equipment. This thesis provides an introduction to battery energy storage system technology, and primarily investigates an EVCS powered via a MVDC bus. A bidirectional DC-DC converter with appropriate controls serves as the interface between the EVCS and the MVDC bus. Two scenarios are investigated for testing and comparing EVCS operation: 1) EVCS power supplied by the interconnected MVDC model and 2) EVCS power supplied by an equivalent voltage source. The ability of the battery charger (synchronous buck converter) to isolate faults in next generation DC power systems is explored. Each of the investigated components is modeled and simulated utilizing the PSCAD simulation environment then analytically validated

Algorithms for Efficient, Resilient, and Economic Operation of Pre-Emptively Reinforced Reconfigurable Distribution Substations

Stochasticity of demand profiles at electricity distribution substations is increasing due to the proliferation of low carbon technologies; in particular mobile, bi-directional, or intermittent loads such as electric vehicles and heat pumps. The decarbonisation of heat and transport will cause a long-term increase in overall connected load, making substation reinforcement necessary, whilst planning of upgrade locations and capacities remains challenging. This project will investigate pre-emptive substation reinforcement with algorithmic topology control, to utilise the additional installed substation capacity only when required. Distribution Substation Dynamic Reconfiguration (DSDR) proposes the installation of additional transformers in parallel with the existing transformer in each substation, removing the need to scrap and replace these. Telematics-controlled switches are installed on the high- and low-voltage side of each transformer in the substation, with local agent algorithms deployed to control in real-time when each parallel transformer is brought into or taken out of service. Substation reconfiguration is thus controlled to optimise for maximum operating efficiency. The threshold algorithm most recently trialled in medium voltage parallel transformer substations is implemented as a baseline, and a novel model-based reconfiguration algorithm is proposed, implemented, and evaluated in software and hardware. This work led to a 1.34% improvement in algorithm performance on substation efficiency, over a yearly demand profile including residential and new electric vehicle load for the year 2050, equivalent to a potential saving of 2.68 TWh annually if deployed UK-wide. This approach unlocks several opportunities to operate existing substations in the smart, flexible, resilient, and efficient manner that will be required to reach the net zero target by 2050