Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

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High-Performance, Energy-Efficient CMOS Arithmetic Circuits

In a modern microprocessor, datapath/arithmetic circuits have always been an important building block in delivering high-performance, energy-efficient computing, because arithmetic operations such as addition and binary number comparison are two of the most commonly used computing instructions. Besides the manufacturing CMOS process, the two most critical design considerations for arithmetic circuits are the logic style and micro-architecture. In this thesis, a constant-delay (CD) logic style is proposed targeting full-custom high-speed applications. The constant delay characteristic of this logic style (regardless of the logic type) makes it suitable for implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. This feature enables a performance advantage over static and dynamic domino logic styles in a single cycle, multi-stage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using a 65-nm general-purpose CMOS technology, the proposed logic style demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders conclude that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. To confirm CD logic's potential, a 148 ps, single-cycle 64-bit adder with CD logic implemented in the critical path is fabricated in a 65-nm, 1-V CMOS process. A new 64-bit Ling adder micro-architecture, which utilizes both inversion and absorption properties to minimize the number of CD logic and the number of logic stage in the critical path, is also proposed. At 1-V supply, this adder's measured worst-case power and leakage power are 135 mW and 0.22 mW, respectively. A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is also proposed. This comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, especially in low input data activity environments. At 65-nm technology with 25% (10%) data activity, the proposed design demonstrates 2.3x (3.5x) and 3.7x (5.8x) power and energy-delay product efficiency, respectively. This comparator is also 2.7x faster at iso-energy (80 fJ) or 3.3x more energy-efficient at iso-delay (200 ps) than existing designs. An improved comparator, where CD logic is utilized in the critical path to achieve high performance without sacrificing the overall energy efficiency, is also realized in a 65-nm 1-V CMOS process. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic

Flexible Ultralow-Power Sensor Interfaces for E-Skin

Thin-film electronics has hugely benefitted from low-cost processes, large-area processability, and multi-functionality. This has not only stimulated innovation in display and sensor technology, but has also demonstrated great potential for integration of components for human-machine interfaces. For electronics to be deployed as sensor interfaces and signal processing, the quest for low power is compelling due to the inherently limited battery lifetime. This review will present the state-of-the-art in thin film electronics and demonstrate examples of low-cost printable transistors and biosensors that are flexible/stretchable for wearable and other applications. Ultralow power design for thin-film transistors will be discussed from the standpoint of reducing both operating voltage and operating current, taking into account the challenges in meeting frequency requirements. Compact models for circuit design will be reviewed along with new insights into ultralow power transistors and high gain amplifier circuits. Finally, a concept for an integrated system comprising sensors and interfacing circuits will be demonstrated, which has the potential to enable battery-less operation.EPSRC under Project EP/M013650/1 EU under Projects DOMINO 645760, 1D-NEON 685758 and BET-EU 692373 IEEE Electron Devices Society PhD Student Fellowship China Scholarship Counci

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

The Integration of nearthreshold and subthreshold CMOS logic for energy minimization

With the rapid growth in the use of portable electronic devices, more emphasis has recently been placed on low-energy circuit design. Digital subthreshold complementary metal-oxide-semiconductor (CMOS) circuit design is one area of study that offers significant energy reduction by operating at a supply voltage substantially lower than the threshold voltage of the transistor. However, these energy savings come at a critical cost to performance, restricting its use to severely energy-constrained applications such as microsensor nodes. In an effort to mitigate this performance degradation in low-energy designs, nearthreshold circuit design has been proposed and implemented in digital circuits such as Intel\u27s energy-efficient hardware accelerator. The application spectrum of nearthreshold and subthreshold design could be broadened by integrating these cells into high-performance designs. This research focuses on the integration of characterized nearthreshold and subthreshold standard cells into high-performance functional modules. Within these functional modules, energy minimization is achieved while satisfying performance constraints by replacing non-critical path logic with nearthreshold and subthreshold logic cells. Specifically, the critical path method is used to bind the timing and energy constraints of the design. The design methodology was verified and tested with several benchmark circuits, including a cryptographic hash function, Skein. An average energy savings of 41.15% was observed at a circuit performance degradation factor of 10. The energy overhead of the level shifters accounted for at least 8.5% of the energy consumption of the optimized circuit, with an average energy overhead of 26.76%. A heuristic approach is developed for estimating the energy savings of the optimized design

A sub-threshold cell library and methodology

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 97-102).Sub-threshold operation is a compelling approach for energy-constrained applications where speed is of secondary concern, but increased sensitivity to process variation must be mitigated in this regime. With scaling of process technologies, random within-die variation has recently introduced another degree of complexity in circuit design. This thesis proposes approaches to mitigate process variation in sub-threshold circuits through device sizing, topology selection and fault-tolerant architecture. This thesis makes several contributions to a sub-threshold circuit design methodology. A formal analysis of device sizing trade-offs between delay, energy, and variability reveals that while minimum size devices provide lowest energy and delay in sub-threshold, their increased sensitivity to random dopant fluctuation may cause functional errors. A proposed variation-driven design approach enables consistent sizing of logic gates and registers for constant functional yield. A yield constraint imposes energy overhead at low power supply voltages and changes the minimum energy operating point of a circuit.(cont.) The optimal supply and device sizing depend on the topology of the circuit and its energy versus VDD characteristic. The analysis resulted in a 56-cell library in 65nm CMOS, which is incorporated in a computer-aided design flow. A test chip synthesized from this library implements a fault-tolerant FIR filter. Algorithmic error detection enables correction of transient timing errors due to delay variability in sub-threshold, and also allows the system frequency to be set more aggressively for the average case instead of the worst case.by Joyce Y.S. Kwong.S.M

A Constant Delay Logic Style - An Alternative Way of Logic Design

High performance, energy efficient logic style has always been a popular research topic in the field of very large scale integrated (VLSI) circuits because of the continuous demands of ever increasing circuit operating frequency. The invention of the dynamic logic in the 80s is one of the answers to this request as it allows designers to implement high performance circuit block, i.e., arithmetic logic unit (ALU), at an operating frequency that traditional static and pass transistor CMOS logic styles are difficult to achieve. However, the performance enhancement comes with several costs, including reduced noise margin,charge-sharing noise, and higher power dissipation due to higher data activity. Furthermore, dynamic logic has gradually lost its performance advantage over static logic due to the increased self-loading ratio in deep-submicron technology (65nm and below) because of the additional NMOS CLK footer transistor. Because of dynamic logic's limitations and diminished speed reward, a slowly rising need has emerged in the past decade to explore new logic style that goes beyond dynamic logic. In this thesis a constant delay (CD) logic style is proposed. The constant delay characteristic of this logic style regardless of the logic expression makes it suitable in implementing complicated logic expression such as addition. Moreover, CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature enables performance advantage over static and dynamic logic styles in a single cycle, multi-stage circuit block. Several design considerations including appropriate timing window width adjustment to reduce power consumption and maintain sufficient noise margin to ensure robust operations are discussed and analyzed. Using 65nm general purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic logic respectively in five different logic expressions. Post layout simulation results of 8-bit ripple carry adders conclude that CD-based design is 39% and 23% faster than the static and dynamic-based adders respectively. For ultra-high speed applications, CD-based design exhibits improved energy, power-delay product, and energy-delay product efficiency compared to static and dynamic counterparts

Design and Implementation of Novel High Performance Domino Logic

This dissertation presents design and implementation of novel high performance domino logic techniques with increased noise robustness and reduced leakages. The speed and overhead area became the primary parameters of choice for fabrication industry that led to invention of clocked logic styles named as Dynamic logic and Domino logic families. Most importantly, power consumption, noise immunity, speed of operation, area and cost are the predominant parameters for designing any kind of digital logic circuit technique with effective trade-off amongst these parameters depending on the situation and application of design. Because of its high speed and low overhead area domino logic became process of choice for designing of high speed application circuits. The concerning issues are large power consumption and high sensitivity towards noise. Hence, there is a need for designing new domino methodology to meet the requirements by overcoming above mentioned drawbacks which led to ample opportunities for diversified research in this field. Therefore, the outcome of research must be able to handle the primary design parameters efficiently. Besides this, the designed circuit must exhibit high degree of robustness towards noise.In this thesis, few domino logic circuit techniques are proposed to deal with noise and sub-threshold leakages. Effect of signal integrity issues on domino logic techniques is studied. Furthermore, having been subjected to process corner analysis and noise analysis, the overall performance of proposed domino techniques is found to be enhanced despite a few limitations that are mentioned in this work. Besides this, lector based domino and dynamic node stabilized techniques are also proposed and are investigated thoroughly. Simulations show that proposed circuits are showing superior performance. In addition to this, domino based Schmitt triggers with various hysteresis phenomena are designed and simulated. Pre-layout and post-layout simulation results are compared for proposed Schmitt trigger. Simulations reveal that proposed Schmitt trigger techniques are more noise tolerant than CMOS counterparts. Moreover, a test chip for domino based Schmitt trigger is done in UMC 180 nm technology for fabrication

메모리 어플리케이션을 위한 빠른 과도 응답 성능을 가지는 디지털 낮은 드롭아웃 레귤레이터 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.In this dissertation, the design of a fast transient response digital low-dropout regulator (DLDO) applicable to next-generation memory systems is discussed. Recent technologies in memory systems mainly aim at high power density and fast data rate. Accordingly, the need for a power converter withstanding a large amount of load current change in a short period is increased. Accordingly, a solution for compensating for a voltage drop that causes significant damage to a memory data input/output is searched according to a periodic clock signal. With this situation, two structures that achieve fast transient response performance under the constraints of memory systems are proposed. To mitigate the transient response degradation under slow external clock conditions, an adaptive two-step search algorithm with event-driven approaches DLDO is proposed. The technique solves the limitations of loop operation time dependent on slow external clocks through a ring-amplifier-based continuous-time comparator. Also, shift register is designed as a circular structure with centralized control of each register to reduce the cost. Finally, the remaining regulation error is controlled by an adaptive successive approximation algorithm to minimize the settling time. Fast recovery and settling time are shown through the measurement of the prototype chip implemented by the 40-nm CMOS process. Next, a digital low dropout regulator for ultra-fast transient response is designed. A slope-detector-based coarse controller to detect, compensate, and correct load current changes occurring at every rising or falling edge of tens to hundreds of megahertz clocks is proposed. Compensation efficiency is increased by the method according to the degree of change in load voltage over time. Furthermore, the LUT-based shift register enables the fast loop response speed of the DLDO. Finally, a bidirectional latch-based driver with fast settling speed and high resolution are proposed. The prototype chip is implemented with a 40-nm CMOS process and achieves effective load voltage recovery through fast transient response performance even with low load capacitance.본 논문은 차세대 메모리 시스템에 적용 가능한 빠른 과도 응답 성능을 가지는 디지탈 낮은 드롭아웃 레귤레이터의 설계에 대해 기술한다. 메모리 시스템의 최근 기술들은 높은 전력 밀도와 빠른 데이터 속도를 주된 목표로 하며 이에 맞추어 단기간, 많은 양의 부하 전류 변화를 견디는 파워 컨버터의 필요성이 높아지고 있다. 이에 주기적인 클락 신호에 따라 메모리 데이터 입출력에 유의미한 손상을 발생시키는 전압 강하를 보상하는 해결 방안을 탐색한다. 이를 통해 메모리 시스템이 가지는 제약조건 하에서 빠른 과도 응답 성능을 달성하는 두 가지 구조를 제안한다. 첫 번째 시연으로서, 느린 외부 클락 조건에서 유발되는 디지탈 낮은 드롭아웃 레귤레이터의 과도 응답 성능 저하를 완화시키기 위한 이벤트 주도 방식의 적응형 두 단계 서치 기술을 제안한다. 본 기술은 느린 외부클락에 의존한 루프 동작 시간의 한계를 고리 증폭기 기반 연속 시간 비교기를 통해 해결한다. 또한 자리 이동 레지스터의 구현에 소모되는 비용을 줄이고자 각 레지스터의 제어 장치를 중앙으로 집적시킨 순환형 구조로 설계되었다. 마지막으로 남아있는 조정 에러는 적응방식의 축차 비교형 알고리즘으로 제어하여 교정에 필요한 시간을 최소화하였다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 부하 전압의 빠른 회복 속도와 정정시간을 보임을 확인하였다. 두 번째 시연으로서, 초고속 과도 응답 환경에 적합한 디지털 낮은 드롭아웃 레귤레이터가 설계되었다. 수십~수백 메가헤르쯔 클락의 상승 또는 하강 엣지마다 발생하는 부하 전류 변화를 탐지하고 보상하고 정정하기 위해 기울기 탐지기 기반 coarse 제어기 기술을 제안한다. 시간에 따른 부하 전압 변화의 정도에 따라 차등 보상하는 알고리즘을 적용함으로써 보상 효율을 높였다. 나아가 순람표 기반 자리이동 레지스터는 부하 전류 과도 상태 이후 디지탈 레귤레이터의 빠른 루프 응답 속도를 가능케 하였다. 마지막으로 남은 조정 에러를 제어하는데 있어서 기존 자리이동 레지스터 방식에서 벗어나 빠른 수렴 속도와 높은 해상도를 가지는 양방향 래치 기반 드라이버가 제안되었다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 낮은 부하 축전용량에도 빠른 과도 응답 성능을 통해 효과적인 부하 전압 회복을 이루어 내었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 VARIOUS TYPES OF LDO 4 1.2.1 ANALOG LDO VS. DIGITAL LDO 4 1.2.2 CAP LDO VS. CAP-LESS LDO 6 1.3 THESIS ORGANIZATION 8 CHAPTER 2 BACKGROUNDS ON DIGITAL LOW-DROPOUT REGULATOR 9 2.1 BASIC DIGITAL LOW-DROPOUT REGULATOR 9 2.2 FAST TRANSIENT RESPONSE LOW-DROPOUT REGULATOR 12 2.2.1 RESPONSE TIME 13 2.2.1 SETTLING TIME 20 2.3 VARIOUS METHODS FOR IMPLEMENT FAST TRANSIENT DIGITAL LDO 21 2.3.1 EVENT-DRIVEN DIGITAL LDO 21 2.3.2 FEEDFORWARD CONTROL 23 2.3.3 COMPUTATIONAL DIGITAL LDO 25 2.4 DESIGN POINTS OF FAST TRANSIENT RESPONSE DIGITAL LDO 27 CHAPTER 3 A FAST DROOP-RECOVERY EVENT-DRIVEN DIGITAL LDO WITH ADAPTIVE LINEAR/BINARY TWO-STEP SEARCH FOR VOLTAGE REGULATION IN ADVANCED MEMORY 29 3.1 OVERVIEW 29 3.2 PROPOSED DIGITAL LDO 32 3.2.1 MOTIVATION 32 3.2.2 ALSC WITH TWO-DIMENSIONAL CIRCULAR SHIFTING REGISTER 36 3.2.3 SBSC WITH SUBRANGE SUCCESSIVE-APPROXIMATION REGISTER 39 3.2.4 STABILITY ANALYSIS 41 3.3 CIRCUIT IMPLEMENTATION 44 3.3.1 TIME-INTERLEAVED RING-AMPLIFIER-BASED COMPARATOR 44 3.3.2 ASYNCHRONOUS 2D CIRCULAR SHIFTING REGISTER 49 3.3.3 SUBRANGE SUCCESSIVE APPROXIMATION REGISTER 51 3.4 MESUREMENT RESULTS 54 CHAPTER 4 A FAST TRANSIENT RESPONSE DIGITAL LOW-DROPOUT REGULATOR WITH SLOPE-DETECTOR-BASED MULTI-STEP CONTROL FOR DIGITAL LOAD APPLICATION 62 4.1 OVERVIEW 62 4.2 PROPOSED DIGITAL LDO 64 4.2.1 MOTIVATION 64 4.2.2 ARCHITECTURE OF DIGITAL LDO 66 4.2.3 SLEW-RATE DEPENDENT COARSE-CONTROL LOOP 69 4.2.4 FINE-CONTROL LOOP 72 4.2.5 CONTROL FOR LOAD-TRANSIENT RESPONSE 74 4.3 CIRCUIT IMPLEMENTATION 77 4.3.1 COMPARATOR-TRIGGERED OSCILLATOR DESIGN 77 4.3.2 SLOPE DETECTOR DESIGN 81 4.3.3 LUT-BASED SHIFT REGISTER DESIGN 84 4.3.4 BI-DIRECTIONAL LATCH-BASED DRIVER DESIGN 86 4.4 MEASUREMENT(SIMULATION) RESULTS 90 CHAPTER 5 CONCLUSION 95 BIBLIOGRAPHY 97 초 록 109박