Energy Efficient Hardware Accelerators for Packet Classification and String Matching

This thesis focuses on the design of new algorithms and energy efficient high throughput hardware accelerators that implement packet classification and fixed string matching. These computationally heavy and memory intensive tasks are used by networking equipment to inspect all packets at wire speed. The constant growth in Internet usage has made them increasingly difficult to implement at core network line speeds. Packet classification is used to sort packets into different flows by comparing their headers to a list of rules. A flow is used to decide a packet’s priority and the manner in which it is processed. Fixed string matching is used to inspect a packet’s payload to check if it contains any strings associated with known viruses, attacks or other harmful activities. The contributions of this thesis towards the area of packet classification are hardware accelerators that allow packet classification to be implemented at core network line speeds when classifying packets using rulesets containing tens of thousands of rules. The hardware accelerators use modified versions of the HyperCuts packet classification algorithm. An adaptive clocking unit is also presented that dynamically adjusts the clock speed of a packet classification hardware accelerator so that its processing capacity matches the processing needs of the network traffic. This keeps dynamic power consumption to a minimum. Contributions made towards the area of fixed string matching include a new algorithm that builds a state machine that is used to search for strings with the aid of default transition pointers. The use of default transition pointers keep memory consumption low, allowing state machines capable of searching for thousands of strings to be small enough to fit in the on-chip memory of devices such as FPGAs. A hardware accelerator is also presented that uses these state machines to search through the payloads of packets for strings at core network line speeds

Predictive multiple sampling algorithm with overlapping integration intervals for linear wide dynamic range integrating image sensors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 163-170).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Machine vision systems are used in a wide range of applications such as security, automated quality control and intelligent transportation systems. Several of these systems need to extract information from natural scenes in the section of the electromagnetic spectrum visible to humans. These scenes can easily have intra-frame illumination ratios in excess of 10⁶ : 1. Solid-state image sensors that can correctly process wide illumination dynamic range scenes are therefore required to ensure correct reliability and performance. This thesis describes a new algorithm to linearly increase the illumination dynamic range of integrating-type image sensors. A user-defined integration time is taken as a reference to create a potentially large set of integration intervals of different duration (the selected integration time being the longest) but with a common end. The light intensity received by each pixel in the sensing array is used to choose the optimal integration interval from the set, while a pixel saturation predictive decision is used to overlap the integration intervals within the given integration time such that only one frame using the optimal integration interval for each pixel is produced. The total integration time is never exceeded. Benefits from this approach are motion minimization, real-time operation, reduced memory requirements, programmable light intensity dynamic range increase and access to incremental light intensity information during the integration time.(cont.) The algorithm is fully described with special attention to the resulting sensor transfer function, the signal-to-noise ratio, characterization of types and effects of errors in the predictive decision, calculation of the optimal integration intervals set given a certain set size, calculation of the optimal number of integration intervals, and impact of the new algorithm to image data compression. An efficient mapping of this algorithm to a CMOS process was done by designing a proof-of-concept integrated circuit in a 0.18[mu]m 1.8V 5-metal layer process. The major components of the chip are a 1/3" VGA (640 x 480) pixel array, a 4bit per pixel memory array, an integration controller array and an analog-to-digital converter/correlated double sampled (ADC/CDS) array. Supporting components include pixel and memory row decoders, memory and converter output digital multiplexers, pixel-to-ADC/CDS analog multiplexer and test structures. The pixels have a fill factor of nearly 50%, as most of the needed system additions and complexity were taken off-pixel. The prototype is fully functional and linearly expands the dynamic range by more than 60dB.by Pablo M. Acosta-Serafini.Ph.D

Exploring Liquid Computing in a Hardware Adaptation : Construction and Operation of a Neural Network Experiment

Future increases in computing power strongly rely on miniaturization, large scale integration, and parallelization. Yet, approaching the nanometer realm poses new challenges in terms of device reliability, power dissipation, and connectivity - issues that have been of lesser concern in today's prevailing microprocessor implementations. It is therefore necessary to pursue the research on alternative computing architectures and strategies that can make use of large numbers of unreliable devices and only have a moderate power consumption. This thesis describes the construction of an experiment dedicated to exploring silicon adaptations of artificial neural network paradigms for their general applicability, power efficiency, and fault-tolerance. The presented setup comprises peripheral electronics, programmable logic, and software to accommodate a mixed-signal CMOS microchip implementing a flexible perceptron with 256 McCulloch-Pitts neurons. This neural network experiment is used to explore a recent strategy that allows to access the power of recurrent network topologies. While it has been conjectured that this liquid computing is suited for hardware implementations, this first time adaptation to a CMOS neural network affirms this claim. Not only feasibility but also tolerance to substrate variations and robustness to faults during operation are demonstrated

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Security of Ubiquitous Computing Systems

The chapters in this open access book arise out of the EU Cost Action project Cryptacus, the objective of which was to improve and adapt existent cryptanalysis methodologies and tools to the ubiquitous computing framework. The cryptanalysis implemented lies along four axes: cryptographic models, cryptanalysis of building blocks, hardware and software security engineering, and security assessment of real-world systems. The authors are top-class researchers in security and cryptography, and the contributions are of value to researchers and practitioners in these domains. This book is open access under a CC BY license

Computationally efficient algorithms and implementations of adaptive deep brain stimulation systems for Parkinson's disease

Clinical deep brain stimulation (DBS) is a tool used to mitigate pharmacologically intractable neurodegenerative diseases such as Parkinson's disease (PD), tremor and dystonia. Present implementations of DBS use continuous, high frequency voltage or current pulses so as to mitigate PD. This results in some limitations, among which there is stimulation induced side effects and shortening of pacemaker battery life. Adaptive DBS (aDBS) can be used to overcome a number of these limitations. Adaptive DBS is intended to deliver stimulation precisely only when needed. This thesis presents work undertaken to investigate, propose and develop novel algorithms and implementations of systems for adapting DBS. This thesis proposes four system implementations that could facilitate DBS adaptation either in the form of closed-loop DBS or spatial adaptation. The first method involved the use of dynamic detection to track changes in local field potentials (LFP) which can be indicative of PD symptoms. The work on dynamic detection included the synthesis of validation dataset using mainly autoregressive moving average (ARMA) models to enable the evaluation of a subset of PD detection algorithms for accuracy and complexity trade-offs. The subset of algorithms consisted of feature extraction (FE), dimensionality reduction (DR) and dynamic pattern classification stages. The combination with the best trade-off in terms of accuracy and complexity consisted of discrete wavelet transform (DWT) for FE, maximum ratio method (MRM) for DR and k-nearest neighbours (k-NN) for classification. The MRM is a novel DR method inspired by Fisher's separability criterion. The best combination achieved accuracy measures: F1-score of 97.9%, choice probability of 99.86% and classification accuracy of 99.29%. Regarding complexity, it had an estimated microchip area of 0.84 mm² for estimates in 90 nm CMOS process. The second implementation developed the first known PD detection and monitoring processor. This was achieved using complementary detection, which presents a hardware-efficient method of implementing a PD detection processor for monitoring PD progression in Parkinsonian patients. Complementary detection is achieved by using a combination of weak classifiers to produce a classifier with a higher consistency and confidence level than the individual classifiers in the configuration. The PD detection processor using the same processing stages as the first implementation was validated on an FPGA platform. By mapping the implemented design on a 45 nm CMOS process, the most optimal implementation achieved a dynamic power per channel of 2.26 μW and an area per channel of 0.2384 mm². It also achieved mean accuracy measures: Mathews correlation coefficient (MCC) of 0.6162, an F1-score of 91.38%, and mean classification accuracy of 91.91%. The third implementation proposed a framework for adapting DBS based on a critic-actor control approach. This models the relationship between a trained clinician (critic) and a neuro-modulation system (actor) for modulating DBS. The critic was implemented and validated using machine learning models, and the actor was implemented using a fuzzy controller. Therapy is modulated based on state estimates obtained through the machine learning models. PD suppression was achieved in seven out of nine test cases. The final implementation introduces spatial adaptation for aDBS. Spatial adaptation adjusts to variation in lead position and/or stimulation focus, as poor stimulation focus has been reported to affect therapeutic benefits of DBS. The implementation proposes dynamic current steering systems as a power-efficient implementation for multi-polar multisite current steering, with a particular focus on the output stage of the dynamic current steering system. The output stage uses dynamic current sources in implementing push-pull current sources that are interfaced to 16 electrodes so as to enable current steering. The performance of the output stage was demonstrated using a supply of 3.3 V to drive biphasic current pulses of up to 0.5 mA through its electrodes. The preliminary design of the circuit was implemented in 0.18 μm CMOS technology