186 research outputs found

    ์˜คํ”„์…‹ ์ œ๊ฑฐ๊ธฐ์˜ ์ ์‘ ์ œ์–ด ๋“ฑํ™”๊ธฐ์™€ ๋ณด์šฐ-๋ ˆ์ดํŠธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋ฅผ ํ™œ์šฉํ•œ ์ˆ˜์‹ ๊ธฐ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021.8. ์—ผ์ œ์™„.In this thesis, designs of high-speed, low-power wireline receivers (RX) are explained. To be specific, the circuit techniques of DC offset cancellation, merged-summer DFE, stochastic Baud-rate CDR, and the phase detector (PD) for multi-level signal are proposed. At first, an RX with adaptive offset cancellation (AOC) and merged summer decision-feedback equalizer (DFE) is proposed. The proposed AOC engine removes the random DC offset of the data path by examining the random data stream's sampled data and edge outputs. In addition, the proposed RX incorporates a shared-summer DFE in a half-rate structure to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm2. Thanks to the AOC engine, the proposed RX achieves the BER of less than 10-12 in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with a 27 dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB. Secondly, a 40 nm CMOS RX with Baud-rate phase-detector (BRPD) is proposed. The RX includes two PDs: the BRPD employing the stochastic technique and the BRPD suitable for multi-level signals. Thanks to the Baud-rate CDRโ€™s advantage, by not using an edge-sampling clock, the proposed CDR can reduce the power consumption by lowering the hardware complexity. Besides, the proposed stochastic phase detector (SPD) tracks an optimal phase-locking point that maximizes the vertical eye opening. Furthermore, despite residual inter-symbol interference, proposed BRPD for multi-level signal secures vertical eye margin, which is especially vulnerable in the multi-level signal. Besides, the proposed BRPD has a unique lock point with an adaptive DFE, unlike conventional Mueller-Muller PD. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.24 mm2. The proposed PAM-4 RX achieves the bit-error-rate less than 10-11 in 48 Gb/s and the power efficiency of 2.42 pJ/b.๋ณธ ๋…ผ๋ฌธ์€ ๊ณ ์†, ์ €์ „๋ ฅ์œผ๋กœ ๋™์ž‘ํ•˜๋Š” ์œ ์„  ์ˆ˜์‹ ๊ธฐ์˜ ์„ค๊ณ„์— ๋Œ€ํ•ด ์„ค๋ช…ํ•˜๊ณ  ์žˆ๋‹ค. ๊ตฌ์ฒด์ ์œผ๋กœ ๋งํ•˜๋ฉด, ์˜คํ”„์…‹ ์ƒ์‡„, ๋ณ‘ํ•ฉ๋œ ์„œ๋จธ๋ฅผ ์‚ฌ์šฉํ•˜๋Š” ๊ฒฐ์ • ํ”ผ๋“œ๋ฐฑ ๋“ฑํ™”๊ธฐ ๊ธฐ์ˆ , ํ™•๋ฅ ์  ๋ณด์šฐ ๋ ˆ์ดํŠธ ํด๋Ÿญ๊ณผ ๋ฐ์ดํ„ฐ ๋ณต์›๊ธฐ, ๊ทธ๋ฆฌ๊ณ  ๋‹ค์ค‘ ๋ ˆ๋ฒจ ์‹ ํ˜ธ์— ์ ํ•ฉํ•œ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋ฅผ ์ œ์•ˆํ•œ๋‹ค. ์ฒซ์งธ๋กœ, ์ ์‘ ์˜คํ”„์…‹ ์ œ๊ฑฐ ๋ฐ ๋ณ‘ํ•ฉ๋œ ์„œ๋จธ๋ฅผ ์‚ฌ์šฉํ•˜๋Š” ๊ฒฐ์ • ํ”ผ๋“œ๋ฐฑ ๋“ฑํ™”๊ธฐ๋ฅผ ๊ฐ–์ถ˜ ์ˆ˜์‹ ๊ธฐ๋ฅผ ์ œ์•ˆํ•œ๋‹ค. ์ œ์•ˆ๋œ ์ ์‘ ์˜คํ”„์…‹ ์ œ๊ฑฐ ์—”์ง„์€ ์ž„์˜์˜ ๋ฐ์ดํ„ฐ ์ŠคํŠธ๋ฆผ์˜ ์ƒ˜ํ”Œ๋ง ๋ฐ์ดํ„ฐ, ์—์ง€ ์ถœ๋ ฅ์„ ๊ฒ€์‚ฌํ•˜์—ฌ ๋ฐ์ดํ„ฐ ๊ฒฝ๋กœ ์ƒ์˜ ์˜คํ”„์…‹์„ ์ œ๊ฑฐํ•œ๋‹ค. ๋˜ํ•œ ํ•˜ํ”„ ๋ ˆ์ดํŠธ ๊ตฌ์กฐ์˜ ๋ณ‘ํ•ฉ๋œ ์„œ๋จธ๋ฅผ ์‚ฌ์šฉํ•˜๋Š” ๊ฒฐ์ • ํ”ผ๋“œ๋ฐฑ ๋“ฑํ™”๊ธฐ๋Š” ์ „๋ ฅ์˜ ์‚ฌ์šฉ๊ณผ ํ•˜๋“œ์›จ์–ด์˜ ๋ณต์žก์„ฑ์„ ์ค„์ธ๋‹ค. 40 nm CMOS ๊ธฐ์ˆ ๋กœ ์ œ์ž‘๋œ ํ”„๋กœํ† ํƒ€์ž… ์นฉ์€ 0.083 mm2 ์˜ ๋ฉด์ ์„ ๊ฐ€์ง„๋‹ค. ์ ์‘ ์˜คํ”„์…‹ ์ œ๊ฑฐ๊ธฐ ๋•๋ถ„์— ์ œ์•ˆ๋œ ์ˆ˜์‹ ๊ธฐ๋Š” 10-12 ๋ฏธ๋งŒ์˜ BER์„ ๋‹ฌ์„ฑํ•œ๋‹ค. ๋˜ํ•œ ์ œ์•ˆ๋œ ์ˆ˜์‹ ๊ธฐ๋Š” 5GHz์—์„œ 27 dB์˜ ๋กœ์Šค๋ฅผ ๊ฐ–๋Š” ์ฑ„๋„์—์„œ 10 Gb/s์˜ ์†๋„์—์„œ 18.6 mW๋ฅผ ์†Œ๋น„ํ•˜๋ฉฐ 0.068 pJ/b/dB์˜ FoM์„ ๋‹ฌ์„ฑํ•˜์˜€๋‹ค. ๋‘๋ฒˆ์งธ๋กœ, ๋ณด์šฐ ๋ ˆ์ดํŠธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๊ฐ€ ์žˆ๋Š” 40 nm CMOS ์ˆ˜์‹ ๊ธฐ๊ฐ€ ์ œ์•ˆ๋˜์—ˆ๋‹ค. ์ˆ˜์‹ ๊ธฐ์—๋Š” ๋‘๊ฐœ์˜ ๋ณด์šฐ ๋ ˆ์ดํŠธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋ฅผ ํฌํ•จํ•œ๋‹ค. ํ•˜๋‚˜๋Š” ํ™•๋ฅ ๋ก ์  ๊ธฐ๋ฒ•์„ ์‚ฌ์šฉํ•˜๋Š” ๋ณด์šฐ ๋ ˆ์ดํŠธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ์ด๋‹ค. ๋ณด์šฐ ๋ ˆ์ดํŠธ ํด๋Ÿญ ๋ฐ์ดํ„ฐ ๋ณต์›๊ธฐ์˜ ์žฅ์  ๋•๋ถ„์— ์—์ง€ ์ƒ˜ํ”Œ๋ง ํด๋Ÿญ์„ ์‚ฌ์šฉํ•˜์ง€ ์•Š์Œ์œผ๋กœ์„œ ํŒŒ์›Œ์˜ ์†Œ๋ชจ์™€ ํ•˜๋“œ์›จ์–ด์˜ ๋ณต์žก์„ฑ์„ ์ค„์˜€๋‹ค. ๋˜ํ•œ ํ™•๋ฅ ์  ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋Š” ์ˆ˜์ง ์•„์ด ์˜คํ”„๋‹์„ ์ตœ๋Œ€ํ™”ํ•˜๋Š” ์ตœ์ ์˜ ์œ„์ƒ ์ง€์ ์„ ์ฐพ์„ ์ˆ˜ ์žˆ์—ˆ๋‹ค. ๋‹ค๋ฅธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋Š” ๋‹ค์ค‘ ๋ ˆ๋ฒจ ์‹ ํ˜ธ์— ์ ํ•ฉํ•œ ๋ฐฉ์‹์ด๋‹ค. ์‹ฌ๋ณผ ๊ฐ„ ๊ฐ„์„ญ์ด ๋‹ค์ค‘ ๋ ˆ๋ฒจ ์‹ ํ˜ธ์— ๋งค์šฐ ์ทจ์•ฝํ•œ ๋ฌธ์ œ๊ฐ€ ์žˆ๋”๋ผ๋„ ์ œ์•ˆ๋œ ๋‹ค์ค‘ ๋ ˆ๋ฒจ ์‹ ํ˜ธ์šฉ ๋ณด์šฐ ๋ ˆ์ดํŠธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋Š” ์ˆ˜์ง ์•„์ด ๋งˆ์ง„์„ ํ™•๋ณดํ•œ๋‹ค. ๊ฒŒ๋‹ค๊ฐ€ ์ œ์•ˆ๋œ ๋ณด์šฐ ๋ ˆ์ดํŠธ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ๋Š” ๊ธฐ์กด์˜ ๋ฎฌ๋Ÿฌ-๋ฎ๋Ÿฌ ์œ„์ƒ ๊ฒ€์ถœ๊ธฐ์™€ ๋‹ฌ๋ฆฌ ์ ์‘ํ˜• ๊ฒฐ์ • ํ”ผ๋“œ๋ฐฑ ๋“ฑํ™”๊ธฐ๊ฐ€ ์žˆ๋”๋ผ๋„ ์œ ์ผํ•œ ๋ฝ ์ง€์ ์„ ๊ฐ–๋Š”๋‹ค. ํ”„๋กœํ† ํƒ€์ž… ์นฉ์€ 0.24mm2์˜ ๋ฉด์ ์„ ๊ฐ€์ง„๋‹ค. ์ œ์•ˆ๋œ PAM-4 ์ˆ˜์‹ ๊ธฐ๋Š” 48 Gb/s์˜ ์†๋„์—์„œ 10-11 ๋ฏธ๋งŒ์˜ BER์„ ๊ฐ€์ง€๊ณ , 2.42 pJ/b์˜ FoM์„ ๊ฐ€์ง„๋‹ค.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 BACKGROUNDS 6 2.1 BASIC ARCHITECTURE IN SERIAL LINK 6 2.1.1 SERIAL COMMUNICATION 6 2.1.2 CLOCK AND DATA RECOVERY 8 2.1.3 MULTI-LEVEL PULSE-AMPLITUDE MODULATION 10 2.2 EQUALIZER 12 2.2.1 EQUALIZER OVERVIEW 12 2.2.2 DECISION-FEEDBACK EQUALIZER 15 2.2.3 ADAPTIVE EQUALIZER 18 2.3 CLOCK RECOVERY 21 2.3.1 2X OVERSAMPLING PD ALEXANDER PD 22 2.3.2 BAUD-RATE PD MUELLER MULLER PD 25 CHAPTER 3 AN ADAPTIVE OFFSET CANCELLATION SCHEME AND SHARED SUMMER ADAPTIVE DFE 28 3.1 OVERVIEW 28 3.2 AN ADAPTIVE OFFSET CANCELLATION SCHEME AND SHARED-SUMMER ADAPTIVE DFE FOR LOW POWER RECEIVER 31 3.3 SHARED SUMMER DFE 37 3.4 RECEIVER IMPLEMENTATION 42 3.5 MEASUREMENT RESULTS 45 CHAPTER 4 PAM-4 BAUD-RATE DIGITAL CDR 51 4.1 OVERVIEW 51 4.2 OVERALL ARCHITECTURE 53 4.2.1 PROPOSED BAUD-RATE CDR ARCHITECTURE 53 4.2.2 PROPOSED ANALOG FRONT-END STRUCTURE 59 4.3 STOCHASTIC PHASE DETECTION PAM-4 CDR 64 4.3.1 PROPOSED STOCHASTIC PHASE DETECTION 64 4.3.2 COMPARISON OF THE STOCHASTIC PD WITH SS-MMPD 70 4.4 PHASE DETECTION FOR MULTI-LEVEL SIGNALING 73 4.4.1 PROPOSED BAUD-RATE PHASE DETECTOR FOR MULTI-LEVEL SIGNAL 73 4.4.2 DATA LEVEL AND DFE COEFFICIENT ADAPTATION 79 4.4.3 PROPOSED PHASE DETECTOR 84 4.5 MEASUREMENT RESULT 88 4.5.1 MEASUREMENT OF THE PROPOSED STOCHASTIC BAUD-RATE PHASE DETECTION 94 4.5.2 MEASUREMENT OF THE PROPOSED BAUD-RATE PHASE DETECTION FOR MULTI-LEVEL SIGNAL 97 CHAPTER 5 CONCLUSION 103 BIBLIOGRAPHY 105 ์ดˆ ๋ก 109๋ฐ•

    Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

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    As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

    High-speed equalization and transmission in electrical interconnections

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    The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm ร— 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10โˆ’11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAXยฎ backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10โˆ’8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

    ์ตœ์ ์— ๊ฐ€๊นŒ์šด ํƒ€์ด๋ฐ ์ ์‘์„ ์œ„ํ•ด ์น˜์šฐ์นœ ๋ฐ์ดํ„ฐ ๋ ˆ๋ฒจ๊ณผ ๋ˆˆ ๊ฒฝ์‚ฌ ๋””ํ…ํ„ฐ๋ฅผ ์‚ฌ์šฉํ•œ ์ตœ๋Œ€ ๋ˆˆํฌ๊ธฐ์ถ”์  ํด๋Ÿญ ๋ฐ ๋ฐ์ดํ„ฐ ๋ณต์›ํšŒ๋กœ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ (๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ์ •๋•๊ท .์ด ๋…ผ๋ฌธ์—์„œ๋Š” ์ตœ์†Œ-๋น„ํŠธ ๋น„ํŠธ ์—๋Ÿฌ์œจ (BER)์— ๋Œ€ํ•œ ์ตœ๋Œ€ ๋ˆˆํฌ๊ธฐ ์ถ”์  CDR (MET-CDR)์˜ ์„ค๊ณ„๊ฐ€ ์ œ์•ˆ๋˜์—ˆ๋‹ค. ์ œ์•ˆ ๋œ CDR ์€ ์ตœ์ ์˜ ์ƒ˜ํ”Œ๋ง ๋‹จ๊ณ„๋ฅผ ์ฐพ๊ธฐ ์œ„ํ•ด ๋ฐ˜๋ณต ์ ˆ์ฐจ๋ฅผ ๊ฐ€์ง„ BER ์นด์šดํ„ฐ ๋˜๋Š” ์•„์ด ๋ชจ๋‹ˆํ„ฐ๊ฐ€ ํ•„ ์š”ํ•˜์ง€ ์•Š๋‹ค. ์—๋Ÿฌ ์ƒ˜ํ”Œ๋Ÿฌ ์ถœ๋ ฅ์— ๊ฐ€์ค‘์น˜๋ฅผ ๋‘์–ด ๋”ํ•˜์—ฌ ์–ป์€ ์น˜์šฐ์นœ ๋ฐ ์ดํ„ฐ ๋ ˆ๋ฒจ (biased dLev) ์€ ์‚ฌ์ „ ์ปค์„œ ISI(pre-cursor ISI) ์˜ ์ •๋ณด๋„ ๊ณ ๋ คํ•œ ๋ˆˆ ๋†’์ด ์ •๋ณด๋ฅผ ์ถ”์ถœํ•œ๋‹ค. ๋ธํƒ€ T ๋งŒํผ์˜ ์‹œ๊ฐ„ ์ฐจ์ด๋ฅผ ๋‘” ์ง€์ ์—์„œ ์ž‘๋™ ํ•˜๋Š” ๋‘ ์ƒ˜ํ”Œ๋Ÿฌ๋Š” ํ˜„์žฌ ๋ˆˆ ๋†’์ด์™€ ๋ˆˆ ๊ธฐ์šธ๊ธฐ์˜ ๊ทน์„ฑ์„ ๊ฐ์ง€ํ•˜๊ณ , ์ด ์ •๋ณด ๋ฅผ ํ†ตํ•ด ์ œ์•ˆํ•˜๋Š” CDR ์€ ๋ˆˆ ๊ธฐ์šธ๊ธฐ๊ฐ€ 0 ์ด๋˜๋Š” ์ตœ๋Œ€ ๋ˆˆ ๋†’์ด๋กœ ์ˆ˜๋ ดํ•œ ๋‹ค. ์ธก์ • ๊ฒฐ๊ณผ๋Š” ์ตœ๋Œ€ ๋ˆˆ ๋†’์ด์™€ ์ตœ์†Œ BER ์˜ ์ƒ˜ํ”Œ๋ง ์œ„์น˜๊ฐ€ ์ž˜ ์ผ์น˜ ํ•จ ์„ ๋ณด์—ฌ์ค€๋‹ค. 28nm CMOS ๊ณต์ •์œผ๋กœ ๊ตฌํ˜„๋œ ์ˆ˜์‹ ๊ธฐ ์นฉ์€ 23.5dB ์˜ ์ฑ„๋„ ์†์‹ค์ด ์žˆ๋Š” ์ƒํƒœ์—์„œ 26Gb/s ์—์„œ ๋™์ž‘ ๊ฐ€๋Šฅํ•˜๋‹ค. 0.25UI ์˜ ์•„์ด ์˜คํ”„๋‹ ์„ ๊ฐ€์ง€๋ฉฐ, 87mW ์˜ ํŒŒ์›Œ๋ฅผ ์†Œ๋น„ํ•œ๋‹ค.In this thesis, design of a maximum-eye-tracking CDR (MET-CDR) for minimum bit error rate (BER) is proposed. The proposed CDR does not require a BER coun-ter or an eye-opening monitor with any iterative procedure to find the near-optimal sampling phase. The biased data-level obtained from the weighted sum of error sampler outputs, UP and DN, extracts the actual eye height information in the presence of pre-cursor ISI. Two samplers operating on two slightly different tim-ings detect the current eye height and the polarity of the eye slope so that the CDR tracks the maximum eye height where the slope becomes zero. Measured results show that the sampling phase of the maximum eye height and that of the mini-mum BER match well. A prototype receiver fabricated in 28 nm CMOS process operates at 26 Gb/s with an eye-opening of 0.25 UI and consumes 87 mW while equalizing 23.5 dB of loss at 13 GHz.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VIII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 RECEIVER FRONT-END 5 2.1.1 CHANNEL 7 2.1.2 EQUALIZER 17 2.1.3 CDR 32 2.2 PRIOR ARTS ON CLOCK RECOVERY 39 2.2.1 BB-CDR 39 2.2.2 BER-BASED CDR 41 2.2.3 EOM-BASED CDR 44 2.3 CONCEPT OF THE PROPOSED CDR 47 CHAPTER 3 MAXIMUM-EYE-TRACKING CDR WITH BIASED DATA-LEVEL AND EYE SLOPE DETECTOR 49 3.1 OVERVIEW 49 3.2 DESIGN OF MET-CDR 50 3.2.1 EYE HEIGHT INFORMATION FROM BIASED DATA-LEVEL 50 3.2.2 EYE SLOPE DETECTOR AND ADAPTATION ALGORITHM 60 3.2.3 ARCHITECTURE AND IMPLEMENTATION 67 3.2.4 VERIFICATION OF THE ALGORITHM 71 3.2.5 ANALYSIS ON THE BIASED DATA-LEVEL 76 3.3 EXPANSION OF MET-CDR TO PAM4 SIGNALING 84 3.3.1 MET-CDR WITH PAM4 84 3.3.2 CONSIDERATIONS FOR PAM4 87 CHAPTER 4 MEASUREMENT RESULTS 89 CHAPTER 5 CONCLUSION 99 APPENDIX A MATLAB CODE FOR SIMULATING RECEIVER WITH MET-CDR 100 BIBLIOGRAPHY 105 ์ดˆ ๋ก 113Docto

    State of the art in chip-to-chip interconnects

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    This thesis presents a study of short-range links for chips mounted in the same package, on printed circuit boards or interposers. Implemented in CMOS technology between 7 and 250 nm, with links that operate at a data rate between 0,4 and 112 Gb/s/pin and with energy efficiencies from 0,3 to 67,7 pJ/bit. The links operate on channels with an attenuation lower than 50 dB. A comparison is made with graphical representations between the different articles that shows the correlation between the different essential metrics of chip-to-chip interconnects, as well as its evolution over the last 20 years.Esta tesis presenta un estudio de enlaces de corto alcance para chips montados en un mismo paquete, en placas de circuito impreso o intercaladores. Implementado en tecnologรญa CMOS entre 7 y 250 nm, con enlaces que operan a una velocidad de datos entre 0,4 y 112 Gb/s/pin y con eficiencias energรฉticas de 0,3 a 67,7 pJ/bit. Los enlaces operan en canales con una atenuaciรณn inferior a 50 dB. Se realiza una comparaciรณn con representaciones grรกficas entre los diferentes artรญculos que muestra la correlaciรณn entre las distintas mรฉtricas esenciales de las interconexiones chip a chip, asรญ como su evoluciรณn en los รบltimos 20 aรฑos.Aquesta tesi presenta un estudi d'enllaรงos de curt abast per a xips muntats en el mateix paquet, en plaques de circuits impresos o interposers. Implementat en tecnologia CMOS entre 7 i 250 nm, amb enllaรงos que funcionen a una velocitat de dades entre 0,4 i 112 Gb/s/pin i amb eficiรจncies energรจtiques de 0,3 a 67,7 pJ/bit. Els enllaรงos funcionen en canals amb una atenuaciรณ inferior a 50 dB. Es fa una comparaciรณ amb representacions grร fiques entre els diferents articles que mostra la correlaciรณ entre les diferents mรจtriques essencials d'interconnexions xip a xip, aixรญ com la seva evoluciรณ en els darrers 20 anys

    High Speed Reconfigurable NRZ/PAM4 Transceiver Design Techniques

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    While the majority of wireline standards use simple binary non-return-to-zero (NRZ) signaling, four-level pulse-amplitude modulation (PAM4) standards are emerging to increase bandwidth density. This dissertation proposes efficient implementations for high speed NRZ/PAM4 transceivers. The first prototype includes a dual-mode NRZ/PAM4 serial I/O transmitter which can support both modulations with minimum power and hardware overhead. A source-series-terminated (SST) transmitter achieves 1.2Vpp output swing and employs lookup table (LUT) control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization (FFE) in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The transmitter is designed to work with a receiver that implements an NRZ/PAM4 decision feedback equalizer (DFE) that employs 1 finite impulse response (FIR) and 2 infinite impulse response (IIR) taps for first post-cursor and long-tail ISI cancellation, respectively. Fabricated in GP 65-nm CMOS, the transmitter occupies 0.060mmยฒ area and achieves 16Gb/s NRZ and 32Gb/s PAM4 operation at 10.4 and 4.9 mW/Gb/s while operating over channels with 27.6 and 13.5dB loss at Nyquist, respectively. The second prototype presents a 56Gb/s four-level pulse amplitude modulation (PAM4) quarter-rate wireline receiver which is implemented in a 65nm CMOS process. The frontend utilize a single stage continuous time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancelation requirement, requiring only a 2-tap pre-cursor feed-forward equalization (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) with one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap is employed to cancel first post-cursor and longtail inter-symbol interference (ISI). The FIR tap direct feedback is implemented inside the CML slicers to relax the critical timing of DFE and maximize the achievable data-rate. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. The receiver consumes 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2- tap FFE transmitter. The experimental results and comparison with state-of-the-art shows superior power efficiency of the presented prototypes for similar data-rate and channel loss. The usage of proposed design techniques are not limited to these specific prototypes and can be applied for any wireline transceiver with different modulation, data-rate and CMOS technology

    Wideband integrated circuits for optical communication systems

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    The exponential growth of internet traffic drives datacenters to constantly improvetheir capacity. Several research and industrial organizations are aiming towardsTbps Ethernet and beyond, which brings new challenges to the field of high-speedbroadband electronic circuit design. With datacenters rapidly becoming significantenergy consumers on the global scale, the energy efficiency of the optical interconnecttransceivers takes a primary role in the development of novel systems. Furthermore,wideband optical links are finding application inside very high throughput satellite(V/HTS) payloads used in the ever-expanding cloud of telecommunication satellites,enabled by the maturity of the existing fiber based optical links and the hightechnology readiness level of radiation hardened integrated circuit processes. Thereare several additional challenges unique in the design of a wideband optical system.The overall system noise must be optimized for the specific application, modulationscheme, PD and laser characteristics. Most state-of-the-art wideband circuits are builton high-end semiconductor SiGe and InP technologies. However, each technologydemands specific design decisions to be made in order to get low noise, high energyefficiency and adequate bandwidth. In order to overcome the frequency limitationsof the optoelectronic components, bandwidth enhancement and channel equalizationtechniques are used. In this work various blocks of optical communication systems aredesigned attempting to tackle some of the aforementioned challenges. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback,are designed and measured, utilizing a state-of-the-art 130 nm InP DHBT technology.A modular equalizer block built in 130 nm SiGe HBT technology is presented. Threeultra-wideband traveling wave amplifiers, a 4-cell, a single cell and a matrix single-stage, are designed in a 250 nm InP DHBT process to test the limits of distributedamplification. A differential VCSEL driver circuit is designed and integrated in a4x 28 Gbps transceiver system for intra-satellite optical communications based in arad-hard 130nm SiGe process

    Design of High-Speed Power-Efficient Transmitter with Time-Based Equalization

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    ๋ณธ ๋…ผ๋ฌธ์€ ๊ณ ์†, ์ €์ „๋ ฅ์œผ๋กœ ๋™์ž‘ํ•˜๋Š” ์œ ์„  ์†ก์‹ ๊ธฐ์˜ ์„ค๊ณ„์— ๋Œ€ํ•ด ์„ค๋ช…ํ•˜๊ณ  ์žˆ๋‹ค. ๋ถ„๋ฆฌ๋˜์ง€ ์•Š์€ ์ถœ๋ ฅ ๋“œ๋ผ์ด๋ฒ„๊ฐ€ ์žˆ๋Š” ์—๋„ˆ์ง€ ํšจ์œจ์ ์ธ ์ „์•• ๋ชจ๋“œ ์†ก์‹ ๊ธฐ๋Š” ์œ„์ƒ ์ง€์—ฐ ๋ถ„์„์„ ๊ธฐ๋ฐ˜์œผ๋กœ ์‹œ๊ฐ„ ์˜์—ญ์—์„œ ์ฑ„๋„ ์†์‹ค์„ ๋ณด์ƒํ•œ๋‹ค. ์ง๋ ฌํ™”๋œ ๋ฐ์ดํ„ฐ ์ŠคํŠธ๋ฆผ์ด ์•„๋‹Œ ์†ก์‹  ํด๋Ÿญ์˜ ์œ„์ƒ์„ ๋ณ€์กฐํ•จ์œผ๋กœ์จ ์ œ์•ˆ๋œ ์†ก์‹ ๊ธฐ๋Š” ๋ฐ์ดํ„ฐ ์˜์กด์  ์ง€ํ„ฐ๋ฅผ ํฌ๊ฒŒ ์ค„์ธ๋‹ค. ์ˆ˜ํ‰ ์•„์ด ์˜คํ”„๋‹์€ ์ „์†ก๋œ ๋ฐ์ดํ„ฐ์˜ ์‹คํ–‰ ๊ธธ์ด์— ๋”ฐ๋ผ ์ œ๋กœ ํฌ๋กœ์‹ฑ ์‹œ๊ฐ„ ๋ณ€๋™์„ ๋ณด์ƒํ•จ์œผ๋กœ์จ ๊ฐœ์„ ๋œ๋‹ค. ์ œ์•ˆ๋œ ๋ฐฉ์‹์€ ํฐ ์‹ ํ˜ธ ๋ฐ ์Šค์œ„์นญ ์ „๋ ฅ์„ ์†Œ๋น„ํ•˜๋Š” ๋งŽ์€ ๋“œ๋ผ์ด๋ฒ„ ์Šฌ๋ผ์ด์Šค๋ฅผ ์ œ๊ฑฐํ•จ์œผ๋กœ์จ ๋“œ๋ผ์ด๋ฒ„ ๋ณต์žก์„ฑ์„ ํฌ๊ฒŒ ์ค„์ธ๋‹ค. ํ”„๋กœํ† ํƒ€์ž… ์นฉ์€ 28 nm CMOS ๊ณต์ •์œผ๋กœ ์ œ์ž‘๋˜์—ˆ์œผ๋ฉฐ 0.045 mm2 ์˜ ์‹ค์ œ ๋ฉด์ ์„ ์ฐจ์ง€ํ•œ๋‹ค. ์ธก์ •๋œ ๊ฒฐ๊ณผ๋Š” ์ œ์•ˆ๋œ ์†ก์‹ ๊ธฐ๊ฐ€ 1.0 V ๊ณต๊ธ‰์—์„œ 440 mVppd์˜ ์ถœ๋ ฅ ์Šค์œ™์œผ๋กœ 22 Gb/s์˜ ์†๋„์—์„œ 0.95 pJ/b์˜ ์—๋„ˆ์ง€ ํšจ์œจ์„ ๋‹ฌ์„ฑํ•จ์„ ๋ณด์—ฌ์ค€๋‹ค. ๋˜ํ•œ ํ”ผํฌ ๋Œ€ ํ”ผํฌ ์ง€ํ„ฐ๋Š” 15.0 dB ์†์‹ค์˜ ์ฑ„๋„์— ๋Œ€ํ•ด ์ œ์•ˆ๋œ ์œ„์ƒ ์ง€์—ฐ ๋ณด์ƒ์„ ํ†ตํ•ด 22 Gb/s์˜ ์†๋„์—์„œ 34 ps์—์„œ 20 ps๋กœ ๊ฐ์†Œ๋œ๋‹ค.In this thesis, a design of high-speed, power-efficient wireline transmitter is reported. An energy-efficient voltage-mode transmitter with an un-segmented output driver equalizes channel loss in the time-domain based on the phase de-lay analysis. By modulating the phase of the transmitting clock rather than the serialized data stream, the proposed transmitter significantly reduces the data-dependent jitter. The horizontal eye-opening is improved by compensating for the zero-crossing time variation dependent on the run-length of the transmitted data. The proposed scheme significantly reduces the driver complexity by elim-inating many driver slices that consume significant signaling and switching power. The prototype chip has been fabricated in a 28-nm CMOS process and occupies an active area of 0.045 mm2. The measured results show that the pro-posed transmitter achieves an energy efficiency of 0.95 pJ/b at 22 Gb/s with an output swing of 440 mVppd at 1.0 V supply. In addition, peak-to-peak jitter is reduced from 34 ps to 20 ps at 22 Gb/s with the proposed phase delay compen-sation over the channel with a 15.0 dB loss.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 FEED-FORWARD EQUALIZATION 7 2.2.1 AMPLITUDE-DOMAIN EQUALIZATION 7 2.2.2 PHASE-DOMAIN EQUALIZATION 12 2.2.3 PULSE-WIDTH MODULATION 18 2.3 ADAPTIVE FEED-FORWARD EQUALIZATION 21 2.3.1 AMPLITUDE-DOMAIN EQUALIZATION 21 2.3.2 PULSE-WIDTH MODULATION 24 CHAPTER 3 DESIGN OF THE TIME-BASED FEED-FORWARD EQUALIZATION OF THE TRANSMITTER 26 3.1 OVERVIEW 26 3.2 BASIC CONCEPT OF TIME-BASED FFE 28 3.2.1 ZERO-CROSSING TIME 28 3.2.2 PHASE DELAY 32 3.2.3 FINDING THE OPTIMUM COEFFICIENT 39 3.2.4 COMPARISON WITH CONVENTIONAL FFE 43 3.3 ADAPTIVE TIME-BASED FFE 50 3.3.1 OVERVIEW 50 3.3.2 BEHAVIORAL MODELING 51 3.3.3 SIMULATION RESULTS 53 3.4 TRANSMITTER IMPLEMENTATION 60 3.4.1 OVERVIEW 60 3.4.2 PHASE MODULATION 62 3.4.3 SERIALIZER AND CLOCK PATH 67 CHAPTER 4 MEASUREMENT 71 4.1 OVERVIEW 71 4.2 EYE DIAGRAM 76 4.3 POWER CONSUMPTION 81 CHAPTER 5 CONCLUSION 84 BIBLIOGRAPHY 86 ์ดˆ ๋ก 92๋ฐ•

    Low Power Analog Processing for Ultra-High-Speed Receivers with RF Correlation

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    Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020aยฎ indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions

    Energy-Efficient Receiver Design for High-Speed Interconnects

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    High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1Eโˆ’12 at โˆ’16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s. Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1Eโˆ’12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency. Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.</p
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