Characterisation and mitigation of long-term degradation effects in programmable logic

Reliability has always been an issue in silicon device engineering, but until now it has been managed by the carefully tuned fabrication process. In the future the underlying physical limitations of silicon-based electronics, plus the practical challenges of manufacturing with such complexity at such a small scale, will lead to a crunch point where transistor-level reliability must be forfeited to continue achieving better productivity. Field-programmable gate arrays (FPGAs) are built on state-of-the-art silicon processes, but it has been recognised for some time that their distinctive characteristics put them in a favourable position over application-specific integrated circuits in the face of the reliability challenge. The literature shows how a regular structure, interchangeable resources and an ability to reconfigure can all be exploited to detect, locate, and overcome degradation and keep an FPGA application running. To fully exploit these characteristics, a better understanding is needed of the behavioural changes that are seen in the resources that make up an FPGA under ageing. Modelling is an attractive approach to this and in this thesis the causes and effects are explored of three important degradation mechanisms. All are shown to have an adverse affect on FPGA operation, but their characteristics show novel opportunities for ageing mitigation. Any modelling exercise is built on assumptions and so an empirical method is developed for investigating ageing on hardware with an accelerated-life test. Here, experiments show that timing degradation due to negative-bias temperature instability is the dominant process in the technology considered. Building on simulated and experimental results, this work also demonstrates a variety of methods for increasing the lifetime of FPGA lookup tables. The pre-emptive measure of wear-levelling is investigated in particular detail, and it is shown by experiment how di fferent reconfiguration algorithms can result in a significant reduction to the rate of degradation

Use case scenarios and preliminary reference model

This document provides the starting point for the development of dependability solutions in the HIDENETS project with the following contents: (1) A conceptual framework is defined that contains the relevant terminology, threats and general requirements. This framework is a HIDENETS relevant subset of existing state-of-the-art views in the scientific dependability community. Furthermore, the dependability framework contains a first list of relevant functionalities in the communication and middleware level, which will act as input for the architectural discussions in HIDENETS work packages (WPs) 2 and 3. (2) A set of 17 applications with HIDENETS relevance is identified and their corresponding dependability requirements are derived. These applications belong mostly to the class of car-tocar and car-to-infrastructure services and have been selected due to their different types of dependability needs. (3) The applications have been grouped in six HIDENETS use cases, each consisting of a set of applications. The use cases will be the basis for the development of the dependability solutions in all other WPs. Together with a description of each use-case, application-specific architectural aspects are identified and corresponding failure modes and challenges are listed. (4) The business impact of dependability solutions for these use cases is analysed. (5) A preliminary definition of a HIDENETS reference model is provided, which contains highlevel architectural assumptions. This HIDENETS reference model will be further developed in the course of the HIDENETS projects in close cooperation with the other WPs, which is the reason why the preliminary version also contains a collection of potential contributions from other WPs that shall be developed and investigated in the course of the HIDENETS project. In summary, the identified use-cases and their requirements clearly show the large number of dependability related challenges. First steps towards technical solutions have been made in this report in the preliminary reference model, whereas the other work-packages have started in the meanwhile to develop such solutions further based on 'middleware technology' (WP2), 'communication protocols' (WP3), 'quantitative analysis methodology' (WP4), and 'design and testing methodology' (WP5

Mobile Ad-Hoc Networks

Being infrastructure-less and without central administration control, wireless ad-hoc networking is playing a more and more important role in extending the coverage of traditional wireless infrastructure (cellular networks, wireless LAN, etc). This book includes state-of-the-art techniques and solutions for wireless ad-hoc networks. It focuses on the following topics in ad-hoc networks: quality-of-service and video communication, routing protocol and cross-layer design. A few interesting problems about security and delay-tolerant networks are also discussed. This book is targeted to provide network engineers and researchers with design guidelines for large scale wireless ad hoc networks

Routerless Network-on-chip

Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures. In this thesis, a new class of on-chip networks, referred to as Routerless (RL) NoCs, where routers are completely eliminated is explored. A novel design that utilizes on-chip wiring resources smartly to achieve comparable hop count and scalability to that of the router-based NoCs is proposed. Several effective techniques that significantly reduce the resource requirement to avoid new network abnormalities in routerless NoC designs are presented. Evaluation results show that, compared with a conventional mesh, the proposed routerless NoC achieves 9.5X reduction in power, 7.2X reduction in area, 2.5X reduction in zero-load packet latency, and 1.7X increase in throughput. In addition, compared with the state-of-the-art low-cost NoC design, the proposed approach achieves 7.7X reduction in power, 3.3X reduction in area, 1.3X reduction in zero-load packet latency, and 1.6X increase in throughput. Moreover, the shrinking features sizes due to technology innovation results in increasing link failure rates. For RL NoC this is a major concern due to a large number of wires that RL NoC employs. To address a solution to this problem, a fault tolerance technique for permanent link failures without using redundant wires is introduced and this technique requires a minimal overhead to the existing RL NoC. The performance of the technique after a fault recovery is extensively assessed using synthetic traffic patterns and PARSEC workloads. On average, latency is increased by 5.2% and 10.03% for synthetic patterns and PARSEC workloads, respectively. Moreover, this technique requires only an additional 4% area and 20.3% of total power

Fault-tolerant satellite computing with modern semiconductors

Miniaturized satellites enable a variety space missions which were in the past infeasible, impractical or uneconomical with traditionally-designed heavier spacecraft. Especially CubeSats can be launched and manufactured rapidly at low cost from commercial components, even in academic environments. However, due to their low reliability and brief lifetime, they are usually not considered suitable for life- and safety-critical services, complex multi-phased solar-system-exploration missions, and missions with a longer duration. Commercial electronics are key to satellite miniaturization, but also responsible for their low reliability: Until 2019, there existed no reliable or fault-tolerant computer architectures suitable for very small satellites. To overcome this deficit, a novel on-board-computer architecture is described in this thesis.Robustness is assured without resorting to radiation hardening, but through software measures implemented within a robust-by-design multiprocessor-system-on-chip. This fault-tolerant architecture is component-wise simple and can dynamically adapt to changing performance requirements throughout a mission. It can support graceful aging by exploiting FPGA-reconfiguration and mixed-criticality.  Experimentally, we achieve 1.94W power consumption at 300Mhz with a Xilinx Kintex Ultrascale+ proof-of-concept, which is well within the powerbudget range of current 2U CubeSats. To our knowledge, this is the first COTS-based, reproducible on-board-computer architecture that can offer strong fault coverage even for small CubeSats.European Space AgencyComputer Systems, Imagery and Medi

Particle Physics Reference Library

This second open access volume of the handbook series deals with detectors, large experimental facilities and data handling, both for accelerator and non-accelerator based experiments. It also covers applications in medicine and life sciences. A joint CERN-Springer initiative, the “Particle Physics Reference Library” provides revised and updated contributions based on previously published material in the well-known Landolt-Boernstein series on particle physics, accelerators and detectors (volumes 21A,B1,B2,C), which took stock of the field approximately one decade ago. Central to this new initiative is publication under full open access