The manufacture and characterisation of microscale magnetic components.

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Characterisation and integration of materials and processes for planar spiral microinductors with permalloy cores

The increasing density of electronics within portable electronic devices provides the motivation to develop more compact power electronics, such as DC-DC converters. Typically, integrated circuits and each passive component, such as inductors, are discreetly packaged and mounted on printed circuit board (PCB), to implement the converter. Hence for further size reduction there has been growing interest for integration schemes such as Power supply in package (PwrSiP). However, the ultimate goal is the monolithic integration of the power supply solution, in an integration scheme known as Power Supply on Chip (PwrSoC). The economic effectiveness of the converter will be determined by the device footprint and number of processing steps required to fabricate the inductor. Hence, the motivation behind this thesis is the need for microinductors with large inductance density (inductance per device footprint) while maintaining low losses, which can be integrated with silicon IC. Furthermore, the need for thick layers will result in issues with yield and reliability of the fabricated device. Hence there is a need to identify, characterise and integrate materials with low residual stress into the microinductor fabrication process. A typical choice of inter-coil dielectric is the photo-definable epoxy SU-8. However, SU-8 suffers from intrinsic issues with high residual stress and adhesion. One possible replacement for SU-8 as a structural and dielectric layer is Parylene-C. The first objective of this thesis proposes a test-bed inductor process, which incorporates Parylene as a structural and dielectric layer and has a short turnaround time of one week. This fabrication process involves the filling of high aspect ratio gaps between copper structures with Parylene and subsequent chemical mechanical planarisation, and a test chip has been designed to characterise these processes. Additionally, Scotch-tape testing has been used to confirm suitable Parylene adhesion to patterned and unpatterned films used in this process. Subsequently, complete microinductors, with magnetic cores, have been fabricated, characterised and benchmarked against other inductor technologies and architectures reported in the literature. Parylene is expected to produce films with low residual stress due to its room temperature deposition process. However, the test-bed inductor process requires thermal treatments up to 140°C. Hence it was necessary to characterise the stress in Parylene films as a result of processing temperature and compare this to stress levels in SU-8 5 and 3005 films. This study has determined the spatial variation of residual stress in Parylene-C and SU-8 films, by combining automated measurements of strain indicator test structures and local nanoindentation measurements of Young’s modulus. These measurements have been used to wafer map strain, Young’s modulus, and subsequently residual stress in these films, as a result of processing parameter variation. It is well known that placing ferromagnetic material in close proximity to current carrying coils can further enhance the measured inductance value. However, the conductive magnetic core is also a source of loss for the microinductor. Hence, magnetic permeability, electrical resistivity and mechanical stress in the magnetic core influence the inductance value, eddy current losses and reliability of the fabricated microinductor, respectively. The ability to characterise these properties on wafer is essential for process control and verification measurements. This thesis details a test chip capable of routine measurements on NiFe films to characterise the spatial variation of these properties. Furthermore, wafer mapping measurements are reported to identify the correlation between high frequency permeability, electrical resistivity, mechanical strain and the chemical composition of two-component Permalloy film (NixFe(100-x)) electroplated on the surface of 100mm silicon wafers. Finally, MEMS-based inductor fabrication processes typically require a number of electrodeposition steps, which require conductive seed layers for the deposition of the coils and magnetic core material. A typical choice of seed layer is copper. However, due to copper’s paramagnetic behaviour (μ = 1) and low electrical resistivity (ρ=6.69μΩ.cm) this layer contributes to eddy current losses, while acting as a thin ‘screening layer’. It is very likely that using a magnetic seed layer, within the magnetic core, will noticeably reduce eddy current related losses. However, detailed systematic experimental studies on any such improvement have not been documented in the literature. This study involves compositional, structural, electrical and magnetic characterisation of Ni80Fe20 films electro-deposited on non-magnetic and magnetic seed layers (i.e. copper and nickel respectively). Mechanical strain test structures and X-ray analysis have been used to characterise the stress levels and structural properties of Ni80Fe20 films electro-deposited on both copper and nickel seed layers. In addition, planar spiral micro-inductors, both with and without patterned magnetic cores, have been fabricated to determine the effect of patterning on their performance. This is in addition to quantifying the improvement in the electrical performance resulting from the enhanced magnetic and resistive contribution provided by magnetic seed layers

A Low Complexity Design Framework for NFC-RFID Inductive Coupled Antennas

International audienc

Electrodeposition and characterisation of thin films for the fabrication of microinductors

Stress in electrochemically deposited (ECD) magnetic films is an important parameter that can have a critical effect on the performance of MEMS devices such as microinductors. This is especially the case when thick layers of materials are required and where it is important to monitor and hence control stress to prevent cracking and delamination. The reliability of devices, therefore, deeply depends on process parameters and conditions used in depositing these materials on silicon wafers. A MEMS technique for measuring stress spatially around such a wafer has been developed and used to characterise the materials involved in the fabrication of a microinductor. This thesis discusses the design and fabrication of test structures, along with a custom built automatic measurement technique to wafer map the spatial variation of strain, on any sized wafers. The effect of agitation on the grain structure of NiFe has been observed to affect strain which were spatially mapped and correlated with the film composition and thickness. Film uniformity were also shown to improve in the absence of agitation in the bath. To further understand the fundamentals of ECD small scale beaker level galvano-static experiments have been employed to use the same test structures fabricated on small Si chips. The effects of hydrogen evolution on film stress and efficiency with the inclusion of boric acid and saccharin, have been discussed. It was concluded that the tensile stress developed in Ni and NiFe films have an inversely proportional relationship with the plating efficiency. The characterisation of electrodeposited copper films is also of importance as copper films are integrated with magnetic materials in the form of windings for microinductors. The variations in recrystallization and evolution of grains of ECD copper, is for the first time demonstrated spatially using the test structures. The effect of additives in bath on film uniformity was investigated and it was observed that with carrier and additive together the three phases of self annealing were more pronounced. Finally the use of these strain test structures have been demonstrated on thick polymer SU-8 films, which is employed as a structural material in microinductors. The effect of UV exposure dose on the cross linking properties of SU-8 has also been studied. It was observed that non-uniformity in the coated film thickness over the wafer can cause variations in the UV exposure during photolithography that effects the cross linking of the polymer hence, inducing different levels of tensile stress in the material. This unique methodology has therefore opened up many possibilities and can be used for characterising newer materials employed in MEMS, fine-tuning the manufacturing processes to achieve set goals in terms of material properties as well as uniformity and gaining a better understanding of the influence of processing conditions on the produced films

Design, manufacture and test of a magnetic encoder

An new eddy current based magnetic position encoder structure is proposed and studied in this thesis. The encoder is composed of one read head and one scale with metal plates placed periodically on a substrate. The read head contains one emitter and two receiver pairs which are all rectangular planar coils. The electromagnetic coupling between the emitter and receivers were affected by the relative position of the scale. A system level analytical model of the proposed encoder structure has been derived, from which three different encoder signals forms were generated. An amplification and synchronous demodulation circuit has been designed and fabricated. The circuit board was used successfully to process the encoder output signals in the measurement. Four PCB encoder prototypes were fabricated. These encoder structures were studied using the ANSYS MaxwellTM software package. The simulated and measured results were compared. The best accuracy performance of the PCB encoder is -15 μm to 15 μm from the simulation results and -35 μm to 25 μm from the corresponding measurement. An alternative manufacturing process of the magnetic encoder based on multilayer Low Temperature Co-fired Ceramic (LTCC) technology has also been presented. The fabrication process of the LTCC encoder and equipment used were described. Two different methods were used to characterise the LTCC encoder with good agreement between all approaches attempted. The best accuracy performance of the LTCC encoder was -30 μm to 25 μm and after lookup table correction the improved accuracy ranged from -10 μm to 10 μm

Ferrite-based micro-inductors for power systems on chip : from material elaboration to inductor optimisation

Les composants passifs intégrés sont des éléments clés pour les futures alimentations sur puce, compactes et présentant des performances améliorées: haut rendement et forte densité de puissance. L'objectif de ce travail de thèse est d'étudier les matériaux et la technologie pour réaliser de bobines à base de ferrite, intégrées sur silicium, avec des faibles empreintes (<4 mm ²) et de faible épaisseur (<250 µm). Ces bobines, dédiées à la conversion de puissance (˜ 1 W) doivent présenter une forte inductance spécifique et un facteur de qualité élevé dans la gamme de fréquence visée (5-10 MHz). Des ferrites de NiZn ont été sélectionnées comme matériaux magnétiques pour le noyau des bobines en raison de leur forte résistivité et de leur perméabilité stable dans la gamme de fréquence visée. Deux techniques sont développées pour les noyaux de ferrite: la sérigraphie d'une poudre synthétisée au laboratoire et la découpe automatique de films de ferrite commerciaux, suivi dans chaque cas du frittage et le placement sur les conducteurs pour former une bobine rectangulaire. Des bobines tests ont été réalisées dans un premier temps afin que la caractérisation puisse être effectuée : les propriétés magnétiques du noyau de ferrite notamment les pertes volumiques dans le noyau sont ainsi extraites. L'équation de Steinmetz a permis de corréler les courbes de pertes mesurées avec des expressions analytiques en fonction de la fréquence et de l'induction. La deuxième phase de la thèse est l'optimisation de la conception de la micro-bobine à base de ferrite, en tenant compte des pertes attendues. L'algorithme générique est utilisé pour optimiser les dimensions de la bobine avec pour objectif ; la minimisation des pertes et l'obtention de la valeur d'inductance spécifique souhaitée, sous faible polarisation en courant. La méthode des éléments finis pour le magnétisme FEMM est utilisée pour modéliser le comportement électromagnétique du composant. La deuxième série de prototypes a été réalisée afin de valider la méthode d'optimisation. En perspective, les procédés de photolithographie de résine épaisse et le dépôt électrolytique sont en cours de développement pour réaliser les enroulements de cuivre épais autour des noyaux de ferrite optimisés et ainsi former le composant complet.On-chip inductors are key passive elements for future power supplies on chip (PwrSoC), which are expected to be compact and show enhanced performance: high efficiency and high power density. The objective of this thesis work is to study the material and technology to realize small size (<4 mm²) and low profile (< 250 µm) ferrite-based on-chip inductor. This component is dedicated to low power conversion (˜ 1 W) and should provide high inductance density and high quality factor at medium frequency range (5-10 MHz). Fully sintered NiZn ferrites are selected as soft magnetic materials for the inductor core because of their high resistivity and moderate permeability stable in the frequencies range of interest. Two techniques are developed for the ferrite cores: screen printing of in-house made ferrite powder and cutting of commercial ferrite films, followed in each case by sintering and pick-and place assembling to form the rectangular toroid inductor. Test inductors were realized first so that the characterization could be carried out to study the magnetic properties of the ferrite core and the volumetric core losses. The core losses were fit from the measured curve with Steinmetz equation to obtain analytical expressions of losses versus frequency and induction. The second phase of the thesis is the design optimization for the on-chip ferrite based inductor, taking into account the expected losses. Genetic algorithm is employed to optimize the inductor design with the objective function as minimum losses and satisfying the specification on the inductance values under weak current-bias condition. Finite element method for magnetics FEMM is used as a tool to calculate inductance and losses. The second run of prototypes was done to validate the optimization method. In perspective, processes of thick-photoresist photolithography and electroplating are being developed to realize the completed thick copper windings surrounding ferrite cores

Microelectronic Design with Integrated Magnetic and Piezoelectric Structures

This thesis investigates the possibility of integrating the standard CMOS design process with additional microstructures enhancing circuit functionalities. More specifically, the thesis faces the problem of miniaturization of magnetic and piezoelectric devices mostly focused on the application field of EH (Energy Harvesting) systems and ultra-low power and ultra-low voltage systems. It shows all the most critical aspects which have to be taken into account during the design process of miniaturized inductors for PwrSoC (Power System on Chip) or transformers. Furthermore it shows that it is possible to optimize the inductance value and also performances by means of a proper choice of the size of the planar core or choosing a different layout shape such as a serpentine shape in place of the classic toroidal one. A new formula for the correct evaluation of the MPL (Magnetic Path Length) was also introduced. Concerning the piezoelectric counterpart, it is focused on the design and simulation of various MEMS PTs based on a SOI (Silicon on Insulator) structure with AlN (Alluminum Nitride) as active piezoelectric element, in perspective of having a SoC with embedded MEMS devices and circuitry. Furthermore it demonstrates for the first time the use of a PT (Piezoelectric Transformer) for ultra-low voltage EH applications. A new boost oscillator based on a discrete PZT (Lead Zirconate Titanate) PT instead of a MT (Magnetic Transformer) has been modelled and tested on a circuit made up by discrete devices, showing performances comparable to commercial solutions like the LTC3108 from Linear. Furthermore this novel boost oscillator has been designed in a 0.35μm technology by ST Microelectronics, showing better performances as intuitively expected by the developed mathematical model of the entire system

Sintering Applications

Sintering is one of the final stages of ceramics fabrication and is used to increase the strength of the compacted material. In the Sintering of Ceramics section, the fabrication of electronic ceramics and glass-ceramics were presented. Especially dielectric properties were focused on. In other chapters, sintering behaviour of ceramic tiles and nano-alumina were investigated. Apart from oxides, the sintering of non-oxide ceramics was examined. Sintering the metals in a controlled atmosphere furnace aims to bond the particles together metallurgically. In the Sintering of Metals section, two sections dealt with copper containing structures. The sintering of titanium alloys is another topic focused in this section. The chapter on lead and zinc covers the sintering in the field of extractive metallurgy. Finally two more chapter focus on the basics of sintering,i.e viscous flow and spark plasma sintering