Efficient modular arithmetic units for low power cryptographic applications

The demand for high security in energy constrained devices such as mobiles and PDAs is growing rapidly. This leads to the need for efficient design of cryptographic algorithms which offer data integrity, authentication, non-repudiation and confidentiality of the encrypted data and communication channels. The public key cryptography is an ideal choice for data integrity, authentication and non-repudiation whereas the private key cryptography ensures the confidentiality of the data transmitted. The latter has an extremely high encryption speed but it has certain limitations which make it unsuitable for use in certain applications. Numerous public key cryptographic algorithms are available in the literature which comprise modular arithmetic modules such as modular addition, multiplication, inversion and exponentiation. Recently, numerous cryptographic algorithms have been proposed based on modular arithmetic which are scalable, do word based operations and efficient in various aspects. The modular arithmetic modules play a crucial role in the overall performance of the cryptographic processor. Hence, better results can be obtained by designing efficient arithmetic modules such as modular addition, multiplication, exponentiation and squaring. This thesis is organized into three papers, describes the efficient implementation of modular arithmetic units, application of these modules in International Data Encryption Algorithm (IDEA). Second paper describes the IDEA algorithm implementation using the existing techniques and using the proposed efficient modular units. The third paper describes the fault tolerant design of a modular unit which has online self-checking capability --Abstract, page iv

Performance evaluation of high speed compressors for high speed multipliers

This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25°C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only

Design and evaluation of a sensor fail-operational control system for a digitally controlled turbofan engine

A self-learning, sensor fail-operational, control system for the TF30-P-3 afterburning turbofan engine was designed and evaluated. The sensor fail-operational control system includes a digital computer program designed to operate in conjunction with the standard TF30-P-3 bill-of-materials control. Four engine measurements and two compressor face measurements are tested. If any engine measurements are found to have failed, they are replaced by values synthesized from computer-stored information. The control system was evaluated by using a realtime, nonlinear, hybrid computer engine simulation at sea level static condition, at a typical cruise condition, and at several extreme flight conditions. Results indicate that the addition of such a system can improve the reliability of an engine digital control system

Thermodynamic analysis and optimization of a scramjet engine with thermal management system

Thermal management of the scramjet engine is one of the key issues of the challenges brought by the development of hypersonic airbreathing vehicles. A Closed Brayton Cycle thermal management system for a regenerative cooled scramjet is introduced with the goal of reducing the hydrogen fuel flow for cooling. Part of the heat absorbed from fuel is converted into other forms of energy to decrease the heat that must be taken away by hydrogen fuel. Reducing this heat increases the fuel heat sink (cooling capacity) without requiring excess fuel for cooling and eliminating the need to search for a new coolant. The proposed thermal cycle reduces the fuel flow for cooling, and this way, the fuel on board assures the cooling requirements for the whole hypersonic vehicle. The basic concept and working principle are introduced: a thermodynamic cycle analysis is performed to demonstrate the system performance gains of Closed Brayton Cycle (CBC) Thermal Management System (TMS) over the conventional system with regenerative cooling. It was shown that the Closed Brayton Cycle Thermal Management Systems presents a high performance gain when compared to conventional regenerative cooling due to the reduction of fuel flow for cooling and additional power output.A evolução dos veículos hipersónicos despoletou diversos desafios, sendo a gestão térmica de um motor scramjet um dos tópicos principais. É apresentado um sistema de gestão térmica designado Closed Brayton Cycle para um motor scramjet regenerativamente arrefecido. Com o objectivo de reduzir o fluxo de combustível para refrigeração do motor e simultaneamente a quantidade de calor que necessita de ser eliminada, uma parte do calor absorvido pelo combustível é convertido em diferentes formas de energia. A redução do fluxo de combustível significa um aumento da capacidade de refrigeração. A necessidade de recorrer a quantidades extra de combustível é eliminada, assim como a necessidade de desenvolvimento de um novo refrigerante. Através da redução do fluxo de combustível para refrigeração, o combustível a bordo da aeronave garante os requisitos de refrigeração para todo o veículo hipersónico. O conceito básico e o principio de operação são apresentados, uma análise termodinámica é efectuada para demonstrar o desempenho do sistema Closed Brayton Cycle relativamente ao sistema convencional com arrefecimento regenerativo. Foi demonstrado que o sistema Closed Brayton Cycle apresenta um ganho de desempenho alto quando comparado com o sistema regenerativo convencional devido à redução do fluxo de combustível e devido também à potência adicional gerada

F100 Multivariable Control Synthesis Program. Computer Implementation of the F100 Multivariable Control Algorithm

As turbofan engines become more complex, the development of controls necessitate the use of multivariable control techniques. A control developed for the F100-PW-100(3) turbofan engine by using linear quadratic regulator theory and other modern multivariable control synthesis techniques is described. The assembly language implementation of this control on an SEL 810B minicomputer is described. This implementation was then evaluated by using a real-time hybrid simulation of the engine. The control software was modified to run with a real engine. These modifications, in the form of sensor and actuator failure checks and control executive sequencing, are discussed. Finally recommendations for control software implementations are presented

Investigation into arithmetic sub-cells for digital multiplication.

A study of several low-power and high-speed (3,2) counter designs is initially presented, then based on these findings, a new 4:2 compressor design is introduced and proven against other existing and newly devised 4:2 compressors using various logic styles. The results obtained with regards to speed, power and size were used to categorize the circuits in terms of individual and cumulative performance characteristics. A complete 16-bit multiplier design which uses a highly efficient layout scheme along with the top performing 4:2 compressor form the above study is presented. A second multiplier using industry standard (3,2) counters in a 4:2 compressor configuration following the same optimized layout scheme is constructed and simulated as a benchmark for comparison to the new design. In order to carry out this investigation, the proper methodology for power measurement in pass-logic circuits was developed and is presented within. This survey offers an unpartisan approach to power measurement, and an accurate reflection of the vantage points of each logic style. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .H69. Source: Masters Abstracts International, Volume: 44-03, page: 1453. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms