Wavelengths switching and allocation algorithms in multicast technology using m-arity tree networks topology

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University London.In this thesis, the m-arity tree networks have been investigated to derive equations for their nodes, links and required wavelengths. The relationship among all parameters such as leaves nodes, destinations, paths and wavelengths has been found. Three situations have been explored, firstly when just one server and the leaves nodes are destinations, secondly when just one server and all other nodes are destinations, thirdly when all nodes are sources and destinations in the same time. The investigation has included binary, ternary, quaternary and finalized by general equations for all m-arity tree networks. Moreover, a multicast technology is analysed in this thesis to transmit data carried by specific wavelengths to several clients. Wavelengths multicast switching is well examined to propose split-convert-split-convert (S-C-S-C) multicast switch which consists of light splitters and wavelengths converters. It has reduced group delay by 13% and 29% compared with split-convert (S-C) and split-convert-split (S-C-S) multicast switches respectively. The proposed switch has also increased the received signal power by a significant value which reaches 28% and 26.92% compared with S-C-S and S-C respectively. In addition, wavelengths allocation algorithms in multicast technology are proposed in this thesis using tree networks topology. Distributed scheme is adopted by placing wavelength assignment controller in all parents’ nodes. Two distributed algorithms proposed shortest wavelength assignment (SWA) and highest number of destinations with shortest wavelength assignment (HND-SWA) algorithms to increase the received signal power, decrease group delay and reduce dispersion. The performance of the SWA algorithm was almost better or same as HND-SWA related to the power, dispersion and group delay but they are always better than other two algorithms. The required numbers of wavelengths and their utilised converters have been examined and calculated for the researched algorithms. The HND-SWA has recorded the superior performance compared with other algorithms. It has reduced number of utilised wavelengths up to about 19% and minimized number of the used wavelengths converters up to about 29%. Finally, the centralised scheme is discussed and researched and proposed a centralised highest number of destinations (CHND) algorithm with static and dynamic scenarios to reduce network capacity decreasing (Cd) after each wavelengths allocation. The CDHND has reduced (Cd) by about 16.7% compared with the other algorithms

Algorithms & implementation of advanced video coding standards

Advanced video coding standards have become widely deployed coding techniques used in numerous products, such as broadcast, video conference, mobile television and blu-ray disc, etc. New compression techniques are gradually included in video coding standards so that a 50% compression rate reduction is achievable every five years. However, the trend also has brought many problems, such as, dramatically increased computational complexity, co-existing multiple standards and gradually increased development time. To solve the above problems, this thesis intends to investigate efficient algorithms for the latest video coding standard, H.264/AVC. Two aspects of H.264/AVC standard are inspected in this thesis: (1) Speeding up intra4x4 prediction with parallel architecture. (2) Applying an efficient rate control algorithm based on deviation measure to intra frame. Another aim of this thesis is to work on low-complexity algorithms for MPEG-2 to H.264/AVC transcoder. Three main mapping algorithms and a computational complexity reduction algorithm are focused by this thesis: motion vector mapping, block mapping, field-frame mapping and efficient modes ranking algorithms. Finally, a new video coding framework methodology to reduce development time is examined. This thesis explores the implementation of MPEG-4 simple profile with the RVC framework. A key technique of automatically generating variable length decoder table is solved in this thesis. Moreover, another important video coding standard, DV/DVCPRO, is further modeled by RVC framework. Consequently, besides the available MPEG-4 simple profile and China audio/video standard, a new member is therefore added into the RVC framework family. A part of the research work presented in this thesis is targeted algorithms and implementation of video coding standards. In the wide topic, three main problems are investigated. The results show that the methodologies presented in this thesis are efficient and encourage

Cavitation induced starvation for piston-ring/liner tribological conjunction

The study investigates the mechanism of ring-liner lubrication in the vicinity of the top and bottom dead centres of an internal combustion engine. Predicting lubricant transient behaviour is critical when the inlet reversal leads to thin films and inherent metal-to-metal interaction. It was found that the cavitation, which is located at the trailing edge of the contact before reversal, briefly survives after reversal as a confined bubble at the leading edge. This depletes the film promoting starvation. Several algorithms were compared. It is concluded that the lubricant film is thinner than initially thought

Digital enhancement techniques for data converters in scaled CMOS technologies

This thesis presents digital enhancement techniques for data converters in advanced technology nodes. With technology scaling, traditional voltage-domain (VD) analog-to-digital converters (ADCs) face two major challenges: (1) reduction of dynamic range due to supply voltage scaling, and (2) decrease in intrinsic gain of transistors which makes high gain amplifier design tough. To address these challenges, a two-stage ADC architecture is presented which uses time-domain quantization to exploit the advantages of technology scaling. The architecture, consisting of a first stage successive approximation register (SAR) and a second stage ring oscillator, is highly digital and scaling friendly. Two prototypes have been developed to validate the proposed architecture. The 40nm CMOS prototype achieves 75.7 dB dynamic range at an excellent Schreier figure-of-merit of 172.2 dB. The proposed architecture has been extended to a capacitance-to-digital converter and a prototype has been developed in 40nm CMOS. The prototype can sense capacitances with a resolution of 1.3fF and has a Walden figure-of-merit of 60 fJ/step which is more than two times better than the current state-of-the-art. This thesis also presents digital techniques to improve performance of continuous-time(CT), delta-sigma digital-to-analog converters (DACs). Recently, CT delta-sigma DACs have received more attention than their discrete, switched-capacitor counterpart mainly because of low power and/or higher speed of operation. However, a critical disadvantage of CT, delta-sigma DACs is their greatly increased sensitivity to inter-symbol interference (ISI) error. To address this shortcoming of CT DACs, this thesis presents several algorithms that can mitigate ISI error simultaneously with static mismatch error. Further, the proposed algorithms are fully digital in nature and as such, are best poised to take maximum advantage of technology scaling. Thus, the techniques presented in this thesis will be important enabling factors in raising the envelope of performance of CT delta-sigma DACs in advanced technology nodes.Electrical and Computer Engineerin

Modeling and real-time control of urban drainage systems: A review

Urban drainage systems (UDS) may be considered large-scale systems given their large number of associated states and decision actions, making challenging their real-time control (RTC) design. Moreover, the complexity of the dynamics of the UDS makes necessary the development of strategies for the control design. This paper reviews and discusses several techniques and strategies commonly used for the control of UDS. Moreover, the models to describe, simulate, and control the transport of wastewater in UDS are also reviewed.This work has been partially supported by Mexichem, Colombia through the project “Drenaje Urbano y Cambio Climático: Hacia los Sistemas de Alcantarillado del Futuro.” Fase II, with reference No. 548-2012, the scholarships of Colciencias No. 567-2012 and 647-2013, and the project ECOCIS (Ref. DPI2013-48243-C2-1-R).Peer Reviewe

Interconnects architectures for many-core era using surface-wave communication

PhD ThesisNetworks-on-chip (NoCs) is a communication paradigm that has emerged aiming to address on-chip communication challenges and to satisfy interconnection demands for chip-multiprocessors (CMPs). Nonetheless, there is continuous demand for even higher computational power, which is leading to a relentless downscaling of CMOS technology to enable the integration of many-cores. However, technology downscaling is in favour of the gate nodes over wires in terms of latency and power consumption. Consequently, this has led to the era of many-core processors where power consumption and performance are governed by inter-core communications rather than core computation. Therefore, NoCs need to evolve from being merely metalbased implementations which threaten to be a performance and power bottleneck for many-core efficiency and scalability. To overcome such intensified inter-core communication challenges, this thesis proposes a novel interconnect technology: the surface-wave interconnect (SWI). This new RF-based on-chip interconnect has notable characteristics compared to cutting-edge on-chip interconnects in terms of CMOS compatibility, high speed signal propagation, low power dissipation, and massive signal fan-out. Nonetheless, the realization of the SWI requires investigations at different levels of abstraction, such as the device integration and RF engineering levels. The aim of this thesis is to address the networking and system level challenges and highlight the potential of this interconnect. This should encourage further research at other levels of abstraction. Two specific system-level challenges crucial in future many-core systems are tackled in this study, which are cross-the-chip global communication and one-to-many communication. This thesis makes four major contributions towards this aim. The first is reducing the NoC average-hop count, which would otherwise increase packet-latency exponentially, by proposing a novel hybrid interconnect architecture. This hybrid architecture can not only utilize both regular metal-wire and SWI, but also exploits merits of both bus and NoC architectures in terms of connectivity compared to other general-purpose on-chip interconnect architectures. The second contribution addresses global communication issues by developing a distance-based weighted-round-robin arbitration (DWA) algorithm. This technique prioritizes global communication to be send via SWI short-cuts, which offer more efficient power dissipation and faster across-the-chip signal propagation. Results obtained using a cycleaccurate simulator demonstrate the effectiveness of the proposed system architecture in terms of significant power reduction, considervii able average delay reduction and higher throughput compared to a regular NoC. The third contribution is in handling multicast communications, which are normally associated with traffic overload, hotspots and deadlocks and therefore increase, by an order of magnitude the power consumption and latency. This has been achieved by proposing a novel routing and centralized arbitration schemes that exploits the SWI0s remarkable fan-out features. The evaluation demonstrates drastic improvements in the effectiveness of the proposed architecture in terms of power consumption ( 2-10x) and performance ( 22x) but with negligible hardware overheads ( 2%). The fourth contribution is to further explore multicast contention handling in a flexible decentralized manner, where original techniques such as stretch-multicast and ID-tagging flow control have been developed. A comparison of these techniques shows that the decentralized approach is superior to the centralized approach with low traffic loads, while the latter outperforms the former near and after NoC saturation