Dynamic adaptive parallel architecture integrates advanced technologies for petaflops-scale computing

Teraflops-scale computing systems are becoming available to an increasingly broad range of users as the performance of the constituent processing elements increases and their relative cost (e.g. per Mflops) decreases. To the original DOE ASCI Red machine has been added the ASCI Blue systems and additional 1 Teraflops commercial systems at key national centers. Clusters of low cost PCs employing COTS network technologies (e.g. Beowulf-class systems) will make peak Teraflops performance available for less than 2M in the near future for certain classes of well behaved problems. Future larger systems include the Japanese Earth Simulator with a peak performance of 40 Teraflops and three larger ASCI systems anticipated to provide peak performance of 10, 30, and 100 Teraflops culminating in 2005. These systems use existing or near term conventional technologies and architectures with some specialized integration logic and networking. While the peak performance goals can be satisfied through this strategy over the next decade, two major challenges confront the high performance computing community: (1) how to aggressively accelerate performance to the operational regime beyond a Petaflops, and (2) how to achieve high efficiency for a wide range of applications. The Hybrid Technology Multithreaded (HTMT) computer is under development by an interdisciplinary team of investigators to address both problems through an innovative combination of advanced technologies and dynamic adaptive architecture. This paper describes the strategy embodied by the HTMT architecture and discusses the key factors that may enable it to achieve two to three orders of magnitude performance with respect to today's largest systems at a cost and power consumption of only a factor of two to three times those same present day systems

Superconducting circuits without inductors based on bistable Josephson junctions

Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, the information representation in magnetic flux severely limits their functional density presenting a long-standing problem. Here we introduce a concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometrical nor kinetic inductance is promising for the deep scaling of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson junctions allowing the representation of information in their Josephson energy. Since the proposed circuits are composed of Josephson junctions only, they can be called all-Josephson junction (all-JJ) circuits. We present a methodology for the design of the circuits consisting of conventional and bistable junctions. We analyze the principles of the circuit functioning, ranging from simple logic cells and ending with an 8-bit parallel adder. The utilization of bistable junctions in the all-JJ circuits is promising in the aspects of simplification of schematics and the decrease of the JJ count leading to space-efficiency

Dynamic adaptive parallel architecture integrates advanced technologies for petaflops-scale computing

Teraflops-scale computing systems are becoming available to an increasingly broad range of users as the performance of the constituent processing elements increases and their relative cost (e.g. per Mflops) decreases. To the original DOE ASCI Red machine has been added the ASCI Blue systems and additional 1 Teraflops commercial systems at key national centers. Clusters of low cost PCs employing COTS network technologies (e.g. Beowulf-class systems) will make peak Teraflops performance available for less than 2M in the near future for certain classes of well behaved problems. Future larger systems include the Japanese Earth Simulator with a peak performance of 40 Teraflops and three larger ASCI systems anticipated to provide peak performance of 10, 30, and 100 Teraflops culminating in 2005. These systems use existing or near term conventional technologies and architectures with some specialized integration logic and networking. While the peak performance goals can be satisfied through this strategy over the next decade, two major challenges confront the high performance computing community: (1) how to aggressively accelerate performance to the operational regime beyond a Petaflops, and (2) how to achieve high efficiency for a wide range of applications. The Hybrid Technology Multithreaded (HTMT) computer is under development by an interdisciplinary team of investigators to address both problems through an innovative combination of advanced technologies and dynamic adaptive architecture. This paper describes the strategy embodied by the HTMT architecture and discusses the key factors that may enable it to achieve two to three orders of magnitude performance with respect to today's largest systems at a cost and power consumption of only a factor of two to three times those same present day systems

New BSFQ circuit designs with wide margins

Recently we have proposed novel Boolean Single-Flux-quantum (BSFQ) circuits, which Just like CMOS circuits support Boolean primitives directly, and do not require local synchronization for each operation cell. However, previous BSFQ AND, OR, and XOR cells suffered from problems with narrow margin, where their critical margins hardly exceeded +/- 10% due to low flux gain. Furthermore, while being suitable for combinational circuits, previous BSFQ NOT cells had initialization problems in sequential circuits. In this paper, new versions of these circuits with simulated margins beyond +/- 30% are proposed. Moreover, a Muller C-element, an error canceller, a destructive read-out (DRO), and a demultiplexer are also newly created. The operation time, parameter margins, and circuit size of these BSFQ cells are comparable to those of the conventional RSFQ cells

Digital Readout and Control of a Superconducting Qubit

In the quest to build a fault-tolerant quantum computer, superconducting circuits based on Josephson junctions have emerged as a leading architecture. Coherence times have increased significantly over the last two decades, and processors with ∼ 50 qubits have been experimentally demonstrated. These systems traditionally utilize microwave frequency control signals, and heterodyne based detection schemes for measurement. Both of these techniques rely heavily on room temperature microwave generators, high-bandwidth lines from room temperature to millikelvin temperatures, and bulky non-reciprocal elements such as cryogenic microwave isolators. Reliance on these elements makes it impractical to scale existing devices up a single order of magnitude, let alone the 5-6 orders of magnitude needed for performing fault-tolerant quantum algorithms. Here, I present results that suggesting superconducting digital logic, namely Single Flux Quantum (SFQ) logic, can replace analog control and measurement techniques, avoiding the significant overhead involved. I describe a scheme for measuring qubits with a device known as a Josephson Photomultiplier (JPM), which crucially stores the result of a qubit measurement in a classical circulating supercurrent within the device and allows for integration with SFQ detection circuitry. This technique is experimentally demonstrated, with single-shot measurement fidelity of 92%. Two methods for accessing this measurement result are presented, one utilizing ballistic fluxons, and another utilizing flux comparison. Initial experimental results of the latter are presented. In addition, I describe a scheme for controlling qubits with sequences of digital SFQ pulses. This method is then used to control a qubit without a microwave signal generator, with results of an average single-qubit gate fidelity of around 95%. When combined, these techniques form a nearly fully digital interface to superconducting qubits, which could allow these systems to scale much more easily