Dimov, Boyko

Mladenov, Valeri

Ortlepp, Thomas

Todorov, Valery

Uhlmann, F. Hermann

Digitale Bibliothek Thüringen

  PROCEEDINGS 11-15 September 2006      FACULTY OF ELECTRICAL ENGINEERING AND INFORMATION SCIENCE    INFORMATION TECHNOLOGY AND ELECTRICAL ENGINEERING - DEVICES AND SYSTEMS, MATERIALS AND TECHNOLOGIES FOR THE FUTURE      Startseite / Index: http://www.db-thueringen.de/servlets/DocumentServlet?id=12391 51. IWK Internationales Wissenschaftliches Kolloquium International Scientific Colloquium Impressum  Herausgeber: Der Rektor der Technischen Universität llmenau  Univ.-Prof. Dr. rer. nat. habil. Peter Scharff  Redaktion: Referat Marketing und Studentische Angelegenheiten  Andrea Schneider   Fakultät für Elektrotechnik und Informationstechnik  Susanne Jakob  Dipl.-Ing. Helge Drumm  Redaktionsschluss: 07. Juli 2006  Technische Realisierung (CD-Rom-Ausgabe):  Institut für Medientechnik an der TU Ilmenau  Dipl.-Ing. Christian Weigel  Dipl.-Ing. Marco Albrecht  Dipl.-Ing. Helge Drumm  Technische Realisierung (Online-Ausgabe):  Universitätsbibliothek Ilmenau    Postfach 10 05 65  98684 Ilmenau  Verlag:   Verlag ISLE, Betriebsstätte des ISLE e.V.  Werner-von-Siemens-Str. 16  98693 llrnenau   © Technische Universität llmenau (Thür.) 2006  Diese Publikationen und alle in ihr enthaltenen Beiträge und Abbildungen sind urheberrechtlich geschützt. Mit Ausnahme der gesetzlich zugelassenen Fälle ist eine Verwertung ohne Einwilligung der Redaktion strafbar.   ISBN (Druckausgabe): 3-938843-15-2 ISBN (CD-Rom-Ausgabe): 3-938843-16-0  Startseite / Index: http://www.db-thueringen.de/servlets/DocumentServlet?id=12391  51st Internationales Wissenschaftliches Kolloquium Technische Universität Ilmenau  September 11 – 15, 2006  V. Mladenov / V. Todorov / B. Dimov / Th. Ortlepp / F. H. Uhlmann    High-Level Design of Asynchronous RSFQ Digital Circuits   INTRODUCTION  According to the authoritative forecast [1], the previously exponential growth of the clock frequency of the silicon chips will slow in the future. One of the most critical reasons for this is that the dominant part of the clock interval is taken by the recharging of the interconnects’ capacitances by the output currents of the gates, and only a small part - by the intrinsic switching speed of the transistors. The speeding up of this recharging process rapidly increases the total dissipated power density, and this effect becomes much worse with the further miniaturization of the interconnects [2]. The latter has motivated the search for alternative techniques allowing more efficient digital information processing.   One of the prospective candidates for this is the Rapid Single-Flux Quantum (RSFQ) technique [3] based on low-temperature superconductors (LTS). There, an entirely new approach for data coding is used - the binary information is carried by picosecond voltage pulses instead of by voltage levels. They are named Single Flux Quantum (SFQ) pulses due to their quantized area:  00)( Φ=⋅∫∞dttU ,        (1)  with Φ0 = 2.07mV⋅ps – a fundamental physical constant named the single flux quantum. The switching element of this technique is the overdamped Josephson junction having nonlinear and nonhysteretic I-V curve. Currently, all superconductive digital circuits are based on the RSFQ technique. Within the modern roadmaps for electronics [1], this technique is considered as a promising alternative to the semiconductor logic due to the following unique features [3]:  • extreme low power consumption - the energy dissipated during one switching of a single Josephson junction is of order of 10-19 Joule, while the signals are communicated via superconductive (i.e. lossless) transmission lines. Thus, the problem with the extreme large power dissipation of the high-integrated semiconductor digital circuits [2] could be overcome; • extreme high operation speed achieved with relatively large lateral dimensions - simple digital RSFQ circuits with micrometer features sizes operating over 100GHz have been demonstrated long ago [4-9]; • intrinsically digital data representation - due to the nature of the flux quantization (1), the different binary states are inherently defined.   Nevertheless, the maximum successfully reached complexity of an RSFQ digital circuit is less than 100 000 Josephson junctions. One of the main reasons for this are the relatively large feature sizes of the modern LTS RSFQ fabrication technologies, making the development of an ultra-fast large-scale synchronous RSFQ application unimaginable [10]. The only possibility to overcome this problem is the implementation of the asynchronous logic approach [11]. An asynchronous circuit [12] is a digital circuit, in which each component reacts to changes on its inputs as these changes arrive, and produces changes on its outputs when it concludes its computation. No clock signal is provided to synchronize the work of the circuit's components, and the coordination between them is performed by some kind of handshaking protocol. In this way, all problems originating from the global clocking of the large-scale synchronous digital circuits are solved.   As already demonstrated in [10], an efficient design of complex digital circuits is possible only at logic level. However, the supporting CAD tools for asynchronous digital design are quite deficient, while a logic-level simulator for asynchronous RSFQ digital circuits is not available at all. Therefore, the aim of this paper is to present our concept for development of a software tool for high-level design and simulation of asynchronous RSFQ digital circuits.   DATA CODING AND HANDSHAKING WITHIN THE ASYNCHRONOUS RSFQ DIGITAL CIRCUTS  About pulse-based data exchange (such is the SFQ data exchange, see (1)), the most reliable communication is provided by the dual-rail (DR) data coding [11-12]. It is schematically shown in Fig. 1.    Fig. 1 Asynchronous dual-rail data exchange between two communicating units.  It uses two lines per bit of information that has to be communicated. The “true” line is used for transmitting logic “1”, whereas the “false” line is used for transmitting logic “0”. A separate line is providing only for the acknowledge signal. A pulse only in the “true” line is used for coding logical “1”; a pulse only in the “false” line is used for coding the logical “0”, while a simultaneous propagation of pulses in both “true” and “false” lines is forbidden. Note, that this communication is delay-insensitive (DI), i.e. works correctly for any delays of the sender, the receiver, and the connecting lines. Another important advantage is that synchronous blocks can be included into the asynchronous architecture (the so-called globally asynchronous locally synchronous circuits). The latter is shown in Fig. 2. Due to its advantages, the DR information coding is the most popular for semiconductor asynchronous logic. Its popularity is even more pronounced within the RSFQ technique. Therefore, we have based our asynchronous RSFQ cell library [13] also on the DR data coding.    Fig. 2 Inclusion of a synchronous logic block within an asynchronous architecture based on the DR data coding.   If a complex asynchronous digital circuit should be designed to be DI, a handshaking feedback should connect each pair of communicating blocks. This is usually done by a Muller-C-element, whose electrical scheme and elements’ values can be found in [13]. This, however, results into complicated circuit’s topology and reduced operation speed, thus making the full-DI design impractical about large-scale circuits. Much simpler and faster circuits result, if the handshaking feedbacks are omitted always when possible. The latter is illustrated by the simple asynchronous circuit in Fig. 3. It contains two branches in parallel – NOR and NOT branch, and AND and NAND branch. To make it DI, one should use two additional Muller C-elements (see Fig 6(b)), increasing the circuit complexity with about 30% and reducing its speed with nearly the same factor.             (a)                                                                          (b)  ANDNOR NOTNANDNOT3NAND2NOR1AND1in1in1_0in4in4_0in3in3_0in2in2_0out1out1_0out2out2_001111100               CCNOTNANDNOT3NAND2NOTANDNORNOR1AND1in1in1_0in4in4_0in3in3_0in2in2_0out1out1_0out2out2_0NOTCC1C201111000100  Fig. 3 Asynchronous DR digital circuit without (a) and with (b) handshaking feedbacks.  Being no more DI, the correct operation of the circuit in Fig. 3(a) depends on certain assumptions about the delay times of the composing gates, whose violation will cause erroneous behaviour. Such behaviour can be avoided already during the design phase, if proper handling of the time-domain characteristics of the gates can be performed. In [14], we have reported on our novel technique for manipulation of the RSFQ time-delays, while in [15] we present our efficient approach for statistical prediction of the RSFQ time-delay spread due to the spread of the technological parameters. In the next section of this paper, we describe our software tool for high-level simulation and verification of asynchronous RSFQ digital circuits, in which these both techniques have been successfully incorporated.   HIGH-LEVEL SIMULATION AND VERIFICATION OF ASYNCHRONOUS RSFQ DIGITAL CIRCUTS  The main problem prohibiting the straightforward high-level simulation and verification of complex asynchronous RSFQ digital circuits is the unique nature of the SFQ data coding. As seen from (1), the SFQ data are carried by picosecond voltage pulses instead of voltage levels as by the classical semiconductors. However, all established tools for high-level design are addressed to the semiconductor electronics, i.e. are not compatible with the SFQ data coding.   Our basic idea to solve this problem is to use a general purpose logic level description language for digital devices, and to adapt it to the specifics of the asynchronous RSFQ electronics. For this, we have chosen the Very high speed integrated circuit hardware description language (VHDL) [16]. It is a part of the powerful commercial tool for logic-level simulation and verification of complex digital circuits ModelSim [17] and is mainly addressed to the level-based synchronous semiconductor electronics. We have elaborated a special approach for VHDL interpretation of DR SFQ data exchange and developed VHDL models of all components of our asynchronous RSFQ cell library [13].   Below, we illustrate this about two of the most complex gates – the DR AND and the DR XOR one. Their schematics, electrical symbols, and true tables are given in Fig. 4 and Fig. 5, respectively, while their elements’ values and operation principles can be found in [13], [11].        Fig. 4 Electrical scheme, electrical symbol, and true table of the asynchronous DR RSFQ AND gate      X Y⊕  X Y⊕      Fig. 5 Electrical scheme, electrical symbol, and true table of the asynchronous DR RSFQ XOR gate  The time-domain behaviour of the both gates, which has been obtained from our high-level simulations, is shown in Fig. 6 and Fig. 7, respectively. They have also been simulated at low level with the freeware simulator for RSFQ circuits JSIM [18] and the resulting oscillograms are also shown in Fig. 6 and Fig. 7. The perfect agreement between the both sets of results demonstrates clearly the exactness of our approach for high-level modelling of the asynchronous RSFQ digital circuits.  X 1 1 0 0 X  0 0 1 1 Y 1 0 1 0 Y  0 1 0 1 XY 1 0 0 0 XY 0 1 1 1 1 2 3 4 X 1  1 0 0 X  0 0 1 1 Y 1 0 1 0 Y  0 1 0 1 X Y⊕ 0 1 1 0 X Y⊕ 1 0 0 1 1 2 3 4       Fig. 6 Input-output signals of the DR RSFQ AND gate, obtained after simulations with JSIM (up) and the VHDL-modelling with ModelSim (down).        X Y⊕  X Y⊕    Fig. 7 Input-output signals of the DR RSFQ XOR gate, obtained after simulations with JSIM (up) and the VHDL-modelling with ModelSim (down).    CONCLUSIONS  We have used the general purpose high-level description language VHDL and elaborated a special approach for VHDL modelling of SFQ data exchange. It has been implemented into a software tool for high-level modelling and simulation of complex asynchronous RSFQ digital circuits. In this tool, we have also implemented our novel technique for manipulation of the RSFQ delay times, allowing asynchronous design with reduced number of handshaking feedbacks. Once the complex circuit is designed, this tool checks for its delay-insensitivity using our novel approach for statistical prediction of the RSFQ delay times. Thus, reliable large-scale asynchronous RSFQ digital circuits with improved operation speed and simplified topology can be developed.    ACKNOWLEDGEMENT  This work is supported by the DAAD PPP-program (contracts DAAD-13/2005 and D/04/08637) between the Ilmenau University of Technology / Germany, and the Technical University of Sofia / Bulgaria.   References: [1] International Technology Roadmap for Semiconductors, http://public.itrs.net [2] L. B. Kish, "End of Moore's Law: Thermal (Noise) Death of Integration in Micro and Nano Electronics," Phys. Lett. A, vol.305, pp.144-149, 2002 [3] K. K. Likharev, V. K. Semenov, "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems," IEEE Trans. Appl. Supercond., vol.1, pp.3-28, 1991 [4] V. K. Kaplunenko, M. I. Khabipov, V. P. Koshelets, K. K. Likharev, O. A. Mukhanov, V. K. Semenov, I. L. Serpuchenko, A. N. Vystavkin, "Experimental Study of the RSFQ Logic Elements," IEEE Trans. Magn., vol.25, pp.861-864, 1989 [5] V. K. Kaplunenko, M. I. Khabipov, V. P. Koshelets, I. L. Serpuchenko, A. N. Vystavkin, "Experimental Study of the Single Flux Quantum Devices," Ext. Abstr. ISEC'89, Tokyo, pp.557-560, 1989 [6] L. V. Filipenko, V. K. Kaplunenko, M. I. Khabipov, V. P. Koshelets, K. K. Likharev, O. A. Mukhanov, S. V. Rylov, V. K. Semenov, A. N. Vystavkin, "Experimental Implementation of Analog-to-Digital Converter Based on the Reversible Ripple Counter," IEEE Trans. Magn., vol.27, pp.2464-2467, 1991 [7] W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens, K. K. Likharev, "Superconductor Digital Frequency Divider Operating up to 750 GHz," Appl. Phys. Lett., vol.73, pp.2817-2819, 1998 [8] W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens, K. K. Likharev, "Rapid Single Flux Quantum T-Flip Flop Operating up to 770 GHz," IEEE Trans. Appl. Supercond., vol.9, pp.3212-3215, 1999 [9] D. K. Brock, A. M. Kadin, A. F. Kirichenko, O. A. Mukhanov, S. Sarwana, J. A. Vivalda, W. Chen, J. E. Lukens, "Retargeting RSFQ Cells to Submicron Fabrication Process," IEEE Trans. Appl. Supercond., vol.11, pp.369-372, 2001 [10] B. Dimov, V. Mladenov, V. Todorov, Th. Ortlepp, F. H. Uhlmann, “Design Aspects of Complex Asynchronous RSFQ Digital Circuits,” this conference [11] B. Dimov, General Restrictions and Their Possible Solutions for the Development of Ultra High-Speed Integrated RSFQ Digital Circuits, Wissenschaftsverlag Ilmenau, Germany, 2005 [12] J. A. Brzozowski, C.-J. H. Seger, Asynchronous Circuits, Springer-Verlag, 1995 [13] http://www4.tu-ilmenau.de/EI/ATE/kryo/asyn/index.htm [14] B. Dimov, V. Mladenov, F. H. Uhlmann, "Asynchronous RSFQ Gates with Flexible Delays," Proc. 48. Internat. Wiss. Kolloquium, 22.-25. Sept. 2003, TU Ilmenau, Germany, pp.387-388, 2003 [15] V. Mladenov, V. Todorov, B. Dimov, Th. Ortlepp, F. H. Uhlmann, “Statistical Description and Optimization of the Time-Domain Parameters of Asynchronous RSFQ Digital Circuits,” this conference [16] Douglas L Perry, VHDL: Programming by Example, McGraw-Hill, 2002 [17] http://www.model.com/ [18] E. S. Fang, T. van Duzer, "A Josephson Integrated Circuit Simulator (JSIM) for Superconductive Electronic Application," Ext. Abstr. 2nd ISEC, Tokyo, Japan, pp.407-410, 1989   Authors:  Prof. Dr. Valeri MLADENOV Ing. Valery TODOROV  Dept. Theoretical Electrical Engineering, Technical University of Sofia 8 Kliment Ohridski St., Sofia-1000, Bulgaria E-mail: valerim@tu-sofia.bg  Dr.-Ing. Boyko DIMOV Dr.-Ing. Dipl.-Math. Thomas ORTLEPP Prof. Dr.-Ing. habil. F. Hermann UHLMANN  RSFQ Design Group, Institute for Information Technology, Ilmenau University of Technology P.O.Box 100565, D-98684 Ilmenau, Germany E-mail: tet@tu-ilmenau.de  

High-level design of asynchronous RSFQ digital circuits

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High-level design of asynchronous RSFQ digital circuits

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