Qubit Data Structures for Analyzing Computing Systems

Qubit models and methods for improving the performance of software and hardware for analyzing digital devices through increasing the dimension of the data structures and memory are proposed. The basic concepts, terminology and definitions necessary for the implementation of quantum computing when analyzing virtual computers are introduced. The investigation results concerning design and modeling computer systems in a cyberspace based on the use of two-component structure are presented.Comment: 9 pages,4 figures, Proceeding of the Third International Conference on Data Mining & Knowledge Management Process (CDKP 2014

Memory management in the programming language ICL

This paper presents the issues involved in implementing the programming language ICL and some of the details of the implementation, with special emphasis on aspects of the data management system. While the structures and algorithms presented here apply to all implementations of ICL, they are particularly relevant to the VAX implementation. This report is not intended to serve as an introduction to programming in ICL nor as a comprehensive guide to its implementation

Genuine lab experiences for students in resource constrained environments: The RealLab with integrated intelligent assessment.

Laboratory activities are indispensable for developing engineering skills. Computer Aided Learning (CAL) tools can be used to enhance laboratory learning in various ways, the latest approach being the virtual laboratory technique that emulates traditional laboratory processes. This new approach makes it possible to give students complete and genuine laboratory experiences in situations constrained by limited resources in the provision of laboratory facilities and infrastructure and/or where there is need for laboratory education, for large classes, with only one laboratory stand. This may especially be the case in countries in transition. Most existing virtual laboratories are not available for purchase. Where they are, they may not be cost friendly for resource constrained environments. Also, most do not integrate any form of assessment structure. In this paper, we present a very cost friendly virtual laboratory solution for genuine laboratory experiences in resource constrained environments, with integrated intelligent assessment

Electronic and photonic switching in the atm era

Broadband networks require high-capacity switches in order to properly manage large amounts of traffic fluxes. Electronic and photonic technologies are being used to achieve this objective both allowing different multiplexing and switching techniques. Focusing on the asynchronous transfer mode (ATM), the inherent different characteristics of electronics and photonics makes different architectures feasible. In this paper, different switching structures are described, several ATM switching architectures which have been recently implemented are presented and the implementation characteristics discussed. Three diverse points of view are given from the electronic research, the photonic research and the commercial switches. Although all the architectures where successfully tested, they should also follow different market requirements in order to be commercialised. The characteristics are presented and the architectures projected over them to evaluate their commercial capabilities.Peer ReviewedPostprint (published version

MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented

MPF: A portable message passing facility for shared memory multiprocessors

The design, implementation, and performance evaluation of a message passing facility (MPF) for shared memory multiprocessors are presented. The MPF is based on a message passing model conceptually similar to conversations. Participants (parallel processors) can enter or leave a conversation at any time. The message passing primitives for this model are implemented as a portable library of C function calls. The MPF is currently operational on a Sequent Balance 21000, and several parallel applications were developed and tested. Several simple benchmark programs are presented to establish interprocess communication performance for common patterns of interprocess communication. Finally, performance figures are presented for two parallel applications, linear systems solution, and iterative solution of partial differential equations

Validation by Measurements of a IC Modeling Approach for SiP Applications

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi