Itseishäiriön Kumoajan Digitaalinen Ohjaus

In traditional wireless communication systems, transmission and reception are divided in either time or frequency domain. In-band full-duplex means that the transmission and reception take place on the same frequency simultaneously, theoretically doubling the spectral efficiency. The most significant challenge in wireless full-duplex communication is the self-interference, which causes the systems own transmission signal to be coupled into the receiver. An analog canceller is designed to remove this self-interference from the reception signal. The cancellation takes place entirely in the RF domain. Any variation in the surroundings of the antenna also affect the self-interference. A control system is required to track these changes and adjust the canceller accordingly. This thesis presents a digital control system for the canceller. The control system is implemented using a field-programmable gate array (FPGA). The canceller and the control system were developed at Tampere University of Technology (TUT) in collaboration with Intel Labs. The project was concluded in January 2016, when the finished setup was delivered to Intel Labs. Using the digital control system, the canceller is capable of canceling up to 68 dB, 66 dB and 63 dB of the self-interference from the reception signal with 20 MHz, 40 MHz and 80 MHz signal bandwidths respectively. Roughly 20 dB of the cancellation originates from the intrinsic attenuation between the transmitter and the receiver. The control system is also capable of reacting and adapting to any changes in the self-interference quickly in order to maintain sufficient cancellation in a dynamic environment

ULTRA-WIDEBAND NONLINEAR ECHO-CANCELLATION

Hybrid fiber coaxial (HFC) networks are used around the world to distribute cable television and broadband internet services to customers. These networks are governed by the Data-Over-Cable Service Interface Specification (DOCSIS) family of standards, with the most recent version at the time of this writing being DOCSIS 3.1. A frequency division duplex (FDD) spectrum is used in DOCSIS 3.1, where the upstream and downstream signals are separated in frequency to eliminate interference. A possible method to increase signal bandwidths is to use a full-duplex (FDX) spectrum, in which the US and DS signals use the same frequencies at the same time. A main challenge faced when implementing FDX in a DOCSIS node is eliminating the interference in the received US signal caused by the transmitted DS signal. One possible method for eliminating the interference is utilizing an echo-canceling algorithm, which predicts the self-interference (SI) based on the known DS signal and cancels it from the received US signal. Although echo-cancellation algorithms exist for fundamentally similar applications, the DOCSIS FDX case is more complicated for two main reasons. First, the DOCSIS node uses a nonlinear power amplifier to amplify the DS signal. Second, the DS signal is an ultra-wideband signal spanning a frequency range of up to 1.2 GHz. Most of the amplifier modeling techniques discussed in the literature were designed for narrowband wireless signals and will have limited performance when used with ultra-wideband signals. This thesis develops an algorithm to characterize the power amplifier and to predict the harmonics it generates for a given DS signal. These predicted harmonics can be used to cancel the SI signal in a full duplex DOCSIS system. The algorithm, which is referred to as the ultra-wideband memory polynomial (UWB-MP) model, is based on the well-known memory polynomial model with adaptations which allow the model to predict harmonics for ultra-wideband signals. Since a direct implementation of the UWB-MP model in an FPGA would result in very high resource usage, system architecture recommendations are provided. Our proposed implementation of the model compensates for harmonics up to and including the 3rd order, which has a power spectrum extending above 3600 MHz. Using the techniques discussed in this thesis, it is shown that a sampling rate of 4 GHz allows for cancellation of the SI signal while providing a reasonable balance between performance and resource usage. Matlab simulations of a DOCSIS node with various parameters and PA simulation models were conducted. The simulations showed that over 75 dB of cancellation of the SI signal is possible in an idealized hardware setup. It is also demonstrated that AWGN injected into the received signal does not reduce the ability of the model to estimate the PA harmonics, although the noise itself cannot be canceled. Further simulations showed that the UWB-MP model could cancel harmonics whose power is much higher than that specified in DOCSIS. Although the UWB-MP model was designed with memory polynomial type PAs in mind, simulation results show that significant cancellation is possible with PAs that are represented by Wiener models as well. Based on the simulation results, we recommend using a filter of length 20 coefficients for each harmonic in the UWB-MP model, and 60 iterations with 500 samples for estimating the coefficients with the least squares method

A study on wireless hearing aids system configuration and simulation

Master'sMASTER OF SCIENC

Peak-to-Average Power Ratio Reduction of DOCSIS 3.1 Downstream Signals

Tone reservation (TR) is an attractive and widely used method for peak-to-average power ratio (PAPR) reduction of orthogonal frequency division multiplexing (OFDM) signals, where both transmitter and receiver agree upon a number of subcarriers or tones to be reserved to generate a peak canceling signal that can reduce the peak power of the transmitted signals. The tones are selected to be mutually exclusive with the tones used for data transmission, which allows the receiver to extract the data symbols without distortions. This thesis presents two novel PAPR reduction algorithms for OFDM signals based on the TR principle, which do not distort the transmitted signals. The first proposed algorithm is performed in the time domain, whereas the second algorithm is a new clipping-and-filtering method. Both algorithms consist of two stages. The first stage, which is done off-line, creates a set of canceling signals based on the settings of the OFDM system. In particular, these signals are constructed to cancel signals at different levels of maximum instantaneous power that are above a predefined threshold. The second stage, which is online and iterative, reduces the signal peaks by using the canceling signals constructed in the first stage. The precalculated canceling signals can be updated when different tone sets are selected for data transmission, accommodating many practical applications. Simulation results show that the proposed algorithms achieve slightly better PAPR reduction performance than the conventional algorithms. Moreover, such performance is achieved with much lower computational complexity in terms of numbers of multiplications and additions per iteration. Among the two proposed algorithms, the time-domain algorithm gives the best peak reduction performance but the clipping-and-filtering algorithm requires considerably less number of multiplications per iteration and can be efficiently implemented using the fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) structure

Full-Duplex Wireless for 6G: Progress Brings New Opportunities and Challenges

The use of in-band full-duplex (FD) enables nodes to simultaneously transmit and receive on the same frequency band, which challenges the traditional assumption in wireless network design. The full-duplex capability enhances spectral efficiency and decreases latency, which are two key drivers pushing the performance expectations of next-generation mobile networks. In less than ten years, in-band FD has advanced from being demonstrated in research labs to being implemented in standards and products, presenting new opportunities to utilize its foundational concepts. Some of the most significant opportunities include using FD to enable wireless networks to sense the physical environment, integrate sensing and communication applications, develop integrated access and backhaul solutions, and work with smart signal propagation environments powered by reconfigurable intelligent surfaces. However, these new opportunities also come with new challenges for large-scale commercial deployment of FD technology, such as managing self-interference, combating cross-link interference in multi-cell networks, and coexistence of dynamic time division duplex, subband FD and FD networks.Comment: 21 pages, 15 figures, accepted to an IEEE Journa

Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays

Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through the skull has prevented ultrasound imaging of the brain. This research is a prime step toward implantable wireless microsystems that use ultrasound to image the brain by bypassing the skull. These microsystems offer autonomous scanning (beam steering and focusing) of the brain and transferring data out of the brain for further processing and image reconstruction. The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their associated integrated electronics in terms of electrical power transfer and acoustic reflection which would potentially lead to more efficient and high-performance systems. A fully wireless architecture for ultrasound imaging is demonstrated for the first time. An on-chip programmable transmit (TX) beamformer enables phased array focusing and steering of ultrasound waves in the transmit mode while its on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB) uplink transmitter minimizes the effect of path loss on the transmitted image data out of the brain. A single-chip application-specific integrated circuit (ASIC) is de- signed to realize the wireless architecture and interface with array elements, each of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser, a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building blocks. Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems. In addition, the effect of matching and electrical termination on CMUT array elements is explored leading to new interface structures to improve bandwidth and sensitivity of CMUT arrays in different operation regions. Comprehensive analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D

Design techniques for low noise and high speed A/D converters

Analog-to-digital (A/D) conversion is a process that bridges the real analog world to digital signal processing. It takes a continuous-time, continuous amplitude signal as its input and outputs a discrete-time, discrete-amplitude signal. The resolution and sampling rate of an A/D converter vary depending on the application. Recently, there has been a growing demand for broadband (>1 MHz), high-resolution (>14bits) A/D converters. Applications that demand such converters include asymmetric digital subscriber line (ADSL) modems, cellular systems, high accuracy instrumentation, and medical imaging systems. This thesis suggests some design techniques for such high resolution and high sampling rate A/D converters. As the A/D converter performance keeps on increasing it becomes increasingly difficult for the input driver to settle to required accuracy within the sampling time. This is because of the use of larger sampling capacitor (increased resolution) and a decrease in sampling time (higher speed). So there is an increasing trend to have a driver integrated onchip along with A/D converter. The first contribution of this thesis is to present a new precharge scheme which enables integrating the input buffer with A/D converter in standard CMOS process. The buffer also uses a novel multi-path common mode feedback scheme to stabilize the common mode loop at high speeds. Another major problem in achieving very high Signal to Noise and Distortion Ratio (SNDR) is the capacitor mismatch in Digital to Analog Converters (DAC) inherent in the A/D converters. The mismatch between the capacitor causes harmonic distortion, which may not be acceptable. The analysis of Dynamic Element Matching (DEM) technique as applicable to broadband data-converters is presented and a novel second order notch-DEM is introduced. In this thesis we present a method to calibrate the DAC. We also show that a combination of digital error correction and dynamic element matching is optimal in terms of test time or calibration time. Even if we are using dynamic element matching techniques, it is still critical to get the best matching of unit elements possible in a given technology. The matching obtained may be limited either by random variations in the unit capacitor or by gradient effects. In this thesis we present layout techniques for capacitor arrays, and the matching results obtained in measurement from a test-chip are presented. Thus we present various design techniques for high speed and low noise A/D converters in this thesis. The techniques described are quite general and can be applied to most of the types of A/D converters

Integrated Self-Interference Cancellation for Full-Duplex and Frequency-Division Duplexing Wireless Communication Systems

From wirelessly connected robots to car-to-car communications, and to smart cities, almost every aspect of our lives will benefit from future wireless communications. While promise an exciting future world, next-generation wireless communications impose requirements on the data rate, spectral efficiency, and latency (among others) that are higher than those for today's systems by several orders of magnitude. Full-duplex wireless, an emergent wireless communications paradigm, breaks the long-held assumption that it is impossible for a wireless device to transmit and receive simultaneously at the same frequency, and has the potential to immediately double network capacity at the physical (PHY) layer and offers many other benefits (such as reduced latency) at the higher layers. Recently, discrete-component-based demonstrations have established the feasibility of full-duplex wireless. However, the realization of integrated full duplex radios, compact radios that can fit into smartphones, is fraught with fundamental challenges. In addition, to unleash the full potential of full-duplex communication, a careful redesign of the PHY layer and the medium access control (MAC) layer using a cross-layer approach is required. The biggest challenge associated with full duplex wireless is the tremendous amount of transmitter self-interference right on top of the desired signal. In this dissertation, new self-interference-cancellation approaches at both system and circuit levels are presented, contributing towards the realization of full-duplex radios using integrated circuit technology. Specifically, these new approaches involve elimination of the noise and distortion of the cancellation circuitry, enhancing the integrated cancellation bandwidth, and performing joint radio frequency, analog, and digital cancellation to achieve cancellation with nearly one part-per-billion accuracy. In collaboration with researchers at higher layers of the stack, a cross-layer approach has been used in our full-duplex research and has allowed us to derive power allocation algorithms and to characterize rate-gain improvements for full-duplex wireless networks. To enable experimental characterization of full-duplex MAC layer algorithms, a cross-layered software-defined full-duplex radio testbed has been developed. In collaboration with researchers from the field of micro-electro-mechanical systems, we demonstrate a multi-band frequency-division duplexing system using a cavity-filter-based tunable duplexer and our integrated widely-tunable self-interference-cancelling receiver

Multifunction Radios and Interference Suppression for Enhanced Reliability and Security of Wireless Systems

Wireless connectivity, with its relative ease of over-the-air information sharing, is a key technological enabler that facilitates many of the essential applications, such as satellite navigation, cellular communication, and media broadcasting, that are nowadays taken for granted. However, that relative ease of over-the-air communications has significant drawbacks too. On one hand, the broadcast nature of wireless communications means that one receiver can receive the superposition of multiple transmitted signals. But on the other hand, it means that multiple receivers can receive the same transmitted signal. The former leads to congestion and concerns about reliability because of the limited nature of the electromagnetic spectrum and the vulnerability to interference. The latter means that wirelessly transmitted information is inherently insecure. This thesis aims to provide insights and means for improving physical layer reliability and security of wireless communications by, in a sense, combining the two aspects above through simultaneous and same frequency transmit and receive operation. This is so as to ultimately increase the safety of environments where wireless devices function or where malicious wirelessly operated devices (e.g., remote-controlled drones) potentially raise safety concerns. Specifically, two closely related research directions are pursued. Firstly, taking advantage of in-band full-duplex (IBFD) radio technology to benefit the reliability and security of wireless communications in the form of multifunction IBFD radios. Secondly, extending the self-interference cancellation (SIC) capabilities of IBFD radios to multiradio platforms to take advantage of these same concepts on a wider scale. Within the first research direction, a theoretical analysis framework is developed and then used to comprehensively study the benefits and drawbacks of simultaneously combining signals detection and jamming on the same frequency within a single platform. Also, a practical prototype capable of such operation is implemented and its performance analyzed based on actual measurements. The theoretical and experimental analysis altogether give a concrete understanding of the quantitative benefits of simultaneous same-frequency operations over carrying out the operations in an alternating manner. Simultaneously detecting and jamming signals specifically is shown to somewhat increase the effective range of a smart jammer compared to intermittent detection and jamming, increasing its reliability. Within the second research direction, two interference mitigation methods are proposed that extend the SIC capabilities from single platform IBFD radios to those not physically connected. Such separation brings additional challenges in modeling the interference compared to the SIC problem, which the proposed methods address. These methods then allow multiple radios to intentionally generate and use interference for controlling access to the electromagnetic spectrum. Practical measurement results demonstrate that this effectively allows the use of cooperative jamming to prevent unauthorized nodes from processing any signals of interest, while authorized nodes can use interference mitigation to still access the same signals. This in turn provides security at the physical layer of wireless communications