Inexpensive programmable computer clock

Clock's computer interface accepts pulses from computer (computer commands) and translates them into control signals for clock, and vice versa. Clock is preset by computer to a fixed number of time pulses, and then started. After fixed number of time pulses has occured, clock reads pulse (via interface) to computer and stops

Synchronizer for random binary data

Simplified binary-data transition detector, for synchronization of relatively noise-free signals, can be used with radio or cable data-control links. It permits reception of binary data in absence of clock signal or self-clocking coder

Multifunction audio digitizer

An illustrative embodiment of the invention includes apparatus which simultaneously produces both direct delta modulation and pulse code modulation. An input signal, after amplification, is supplied to a window comparator which supplies a polarity control signal to gate the output of a clock to the appropriate input of a binary up-down counter. The control signals provide direct delta modulation while the up-down counter output provides pulse code modulation

Digital communication system

A digital communication system is reported for parallel operation of 16 or more transceiver units with the use of only four interconnecting wires. A remote synchronization circuit produces unit address control words sequentially in data frames of 16 words. Means are provided in each transceiver unit to decode calling signals and to transmit calling and data signals. The transceivers communicate with each other over one data line. The synchronization unit communicates the address control information to the transceiver units over an address line and further provides the timing information over a clock line. A reference voltage level or ground line completes the interconnecting four wire hookup

High dynamic global positioning system receiver

A Global Positioning System (GPS) receiver having a number of channels, receives an aggregate of pseudorange code time division modulated signals. The aggregate is converted to baseband and then to digital form for separate processing in the separate channels. A fast fourier transform processor computes the signal energy as a function of Doppler frequency for each correlation lag, and a range and frequency estimator computes estimates of pseudorange, and frequency. Raw estimates from all channels are used to estimate receiver position, velocity, clock offset and clock rate offset in a conventional navigation and control unit, and based on the unit that computes smoothed estimates for the next measurement interval

Closed Loop solar array-ion thruster system with power control circuitry

A power control circuit connected between a solar array and an ion thruster receives voltage and current signals from the solar array. The control circuit multiplies the voltage and current signals together to produce a power signal which is differentiated with respect to time. The differentiator output is detected by a zero crossing detector and, after suitable shaping, the detector output is phase compared with a clock in a phase demodulator. An integrator receives no output from the phase demodulator when the operating point is at the maximum power but is driven toward the maximum power point for non-optimum operation. A ramp generator provides minor variations in the beam current reference signal produced by the integrator in order to obtain the first derivative of power

A High Voltage CCD Sensor Control Chip for the Large Synoptic Survey Telescope (LSST)

This thesis presents the design of a Sensor Control Chip (SCC) developed to provide the required clock and bias signals for the Large Synoptic Survey Telescope’s CCD imagers. The circuit consists of current-summing DACs followed by trans-impedance operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCDs. The ASIC is designed to drive clock signals with 20-V adjustable output voltage swing and a maximum output current of 150 mA. The prototype chip has been fabricated in a 0.8-um BCD-SOI process, and is designed to operate down to 175K. Design techniques used in the ASIC will be presented, along with room temperature and operational temperature test results obtained from prototype chips. Test results have shown that the prototype chip is fully functional and agrees well with simulation results

Coordinated transcriptional regulation between a reactive oxygen species-responsive gene network and the circadian clock in Arabidopsis thaliana : a thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Plant Biology at Massey University, Plant Biology, New Zealand

Most organisms have evolved endogenous biological clocks as internal timekeepers to fine-tune physiological processes to the external environment. Energetic cycles such as photosynthesis and glycolytic cycles are physiological processes that have been shown to be under clock control. This work sought to understand the mechanism of the synchrony between the circadian oscillator and products of energetic cycles. The fact that plants rely on photosynthesis for survival,and that photosynthesis relies on the sun, this would have meant that oxygen levels would have fluctuated across the day. A common by-product of oxygen metabolism and photosynthesis is the Reactive Oxygen Species(ROS). Evidence has proposed ROS as regulators of cellular signaling and plant development. However, if ROS levels are left unmanaged, it may cause oxidative stress in organisms, which could damage cellular components and disrupt normal mechanisms of cellular signaling. Therefore, it is advantageous for plants to be able to anticipate such periodic burst in ROS. My research investigates the role of the circadian clock in regulating ROS homeostasis in the model plant Arabidopsis thaliana. I found that ROS production and scavenging wax and wane in a periodic manner under diurnal and circadian conditions. Not only that, at the transcriptional level, ROS7 responsive genes exhibited time-of-day specific phases under diurnal and circadian conditions,suggesting the role of the circadian clock in ROS signaling. Mutations in the core-clock regulator, CIRCADIAN3 CLOCK3 ASSOCIATED3 1 (CCA1), affect both the transcriptional regulation of ROS genes and ROS homeostasis. Furthermore, mis- expressions of other clock genes such as EARLY3 FLOWERING3 33 (ELF3), LUX3 ARRHYTHMO3 (LUX) and TIMING3 OF3 CAB3 EXPRESSION3 13 (TOC1) also have profound effects on ROS signaling and homeostasis, thus suggesting a global clock effect on ROS networks. Taken together, CCA1 is proposed as a master regulator of ROS signaling where the response to oxidative stress is dependent on the time of CCA1 expression. Plants exhibit the strongest response at dawn, the time when CCA1 peaks. Moreover, CCA1 can associate to the Evening Element or CCA17Binding Site on promoters of ROS genes in vivo to coordinate transcription. A common feature of circadian clocks is the presence of multiple interlocked transcriptional feedback loops. It is shown here that the oscillator incorporates ROS as a component of the loop where ROS signals could feed back to affect circadian behavior by changing CCA1 and TOC1 transcription. The clock regulates a plethora of output pathways; particularly the transcription of an output gene FLAVIN3BINDING3KELCH3REPEAT3FHBOX31(FKF1) is affected by ROS signals. Temporal coordination of ROS signaling by CCA1 and the reciprocal control of circadian behavior by ROS revealed a mechanistic link of which plants match their physiology to the environment to confer fitness.Page v (Acknowledgements) has been removed from the published version at the author's request

Design Of 1K Asynchronous Static Random Access Memory Using 0.35 Micron Complementary Metal Oxide Semiconductor Technology

Static Random Access Memory (SRAM) is a high speed semiconductor memory which is widely used as cache memory in microprocessors and microcontrollers, telecommunication and networking devices. The SRAM operations are categorized into two main groups: asynchronous and synchronous. A synchronous SRAM has external clock input signal to control all the memory operation synchronously at either positive or negative edge of the clock signal. While, in asynchronous SRAM, the memory events are not referred or controlled by the external clock. In this study, we have proposed an asynchronous SRAM which configured with a self-holding system in the control unit. The self-holding SRAM control system can produce appropriate signals internally to operate the SRAM system automatically, eliminating hold and wait time, and eliminating Sense Enable and Output Enable signals which usually used in SRAM control system. All input signals are synchronized by the internal control unit. The overall SRAM operations however do not depend on the rising of falling edge of the global (external) clock signal, and thus, the design is still categorized under asynchronous SRAM. The proposed self-holding control system has been developed for a 1 kilobit SRAM using MIMOS 0.35 micron 3.3V CMOS technology Due to limited computer resources such as speed and space, the design had been limited to 1 kilobit memory size. The design covers both schematic and layout designs using Hspice and Cadence Layout Editor, respectively. Meanwhile analysis covers Hspice, Timernill and LVS (Layout versus Schematic). The simulation results have shown the self-holding SRAM control system was working successfully. The design operation speed was 7.0% faster as compared to the SRAM system without the self-holding circuit. An operation speed of 66Mhz with access time of 2.85ns was achieved