Clock's computer interface accepts pulses from computer (computer commands) and translates them into control signals for clock, and vice versa. Clock is preset by computer to a fixed number of time pulses, and then started. After fixed number of time pulses has occured, clock reads pulse (via interface) to computer and stops

Vrancik, J. E.

English

NASA Technical Reports Server

December 1973	 B73-10308 
•
	 NASA TECH BRIEF 
Lewis Research Center 
NASA Tech Briefs announce now technology derived from the U.S. space program. They are issued to encourage 
commercial application. Tech Briefs are available on a subscription basis from the National Technical Information 
Service, Springfield, Virginia 22151. Requests for individual copies or questions relating to the Tech Brief program may 
be directed to the Technology Utilization Office, NASA, Code KT, Washington, D.C. 20546. 
Inexpensive Programmable Computer Clock 
TOT 2 
or 
110 preset 
An inexpensive interval timer clock, complete with a 
computer interface, has been developed that can be 
programmed by a computer. 
Communication with a computer is accomplished by 
devices such as teletypes, line printers, tape readers, etc. 
To the computer, each device must have a name and often 
two names to distinguish the direction of data flow. Along 
with a name, it must have a means of transmitting data. 
This is accomplished by the computer interface whose 
logic components provide electrical and communication 
compatability between the clock and computer.
There are two popular fundamentally different tech-
niques used to communicate with a computer. The first 
mode can be called the wait mode. It involves giving a 
device a command and then waiting until the command 
has been executed and the results are available. However, 
most input-output (I/O) devices are extremely slow 
compared to the computer speed, and thus computer time 
is not utilized efficiently. 
The second mode of communication is the interrupt 
mode. In this mode, the computer again issues a command 
but does not wait for execution. Instead, it may continue 
(continued overleaf) 
This document was prepared under the sponsorship of the National 	 Government assumes any liability resulting from the use of the 
Aeronautics and Space Administration. Neither the United States 	 information contained in this document, or warrants that such use 
Government nor any person acting on behalf of the United States 	 will be free from privately owned rights.
https://ntrs.nasa.gov/search.jsp?R=19730000308 2020-03-17T06:59:32+00:00Z
to execute other instructions. The interrupt mode capa-
bility can be turned on and off by the stored pro-
gramming and other written routines. The actual opera-
tion of the interrupt is governed by clock programming. 
The programmable computer clock can use either of these 
modes of communication. 
The clock's computer interface accepts pulses from the 
computer (computer commands) and translates them into 
control signals for the clock, and vice versa. The clock is 
preset by the computer to a fixed number of time pulses, 
and then started. After the fixed number of time pulses 
has occurred, the clock reads a pulse (via the interface) to 
the computer and stops. 
The general scheme of the programmable clock is 
shown in the figure. An I/O (op-code instruction) preset 
pulse or an 10T2 (input-output transfer pulse) clears the 
flag, resets the on-off switch, and clears the counter. In 
programming, the usual technique would be to issue an 
10T2, load the accumulator with the complement of the 
number of oscillator pulses desired and issue an 10T4. The 
10T4 opens the gate between the accumulator and the 
preset terminals of the counter for 500 nanoseconds. This 
presets the counter. The 10T4 also turns on the on-off 
switch allowing the oscillator pulses to be counted by the 
counter. When the flag becomes set, the interrupt request 
line is grounded and an interrupt will occur. Interrogation 
of the flag by an IOT1 will indicate the clock has caused 
the interrupt and may be reset if desired. In either case, an 
10T2 would be issued to clear the counter, reset the flag, 
and stop the counter. If the flag is left set, it will give a 
false indication of an interrupt if the interrupt is turned 
on or if an lOT 1 is issued. 
The three clock instructs are: skip on flag; clear the 
flag, clear the clock and stop the clock; and preset the 
counter with the contents of the accumulator and start 
the clock. The clock counts at a rate determined by the 
external oscillator and causes an interrupt and sets a flag 
when a 12-bit overflow occurs. 
The clock was tested on a (DEC) PDP-12 computer and 
operated correctly as designed.
Notes: 
1. While the clock was designed to be used with a 12-bit 
capacity computer, slight modifications can be made to 
permit its use on larger machines and logic shifting can 
be made to make it compatible with any computer. 
2. The clock can be built for a total parts cost of less than 
$100 including power supply and I/O connector. 
3. Further information is available in the following 
report: 
NASA TM-X-2500 (N72-16146), Inexpensive Pro-
grammable Clock for a 12-Bit Computer 
Copies may be obtained at cost from: 
Aerospace Research Applications Center 
Indiana University 
400 East Seventh Street 
Bloomington, Indiana 47401 
Telephone: 812-337-7833 
Reference: B73.10308 
4. Specific technical questions may be directed to: 
Technology Utilization Officer 
Lewis Research Center 
21000 Brookpark Road 
Cleveland, Ohio 44135 
Reference: B73-10308 
Patent Status: 
Inquiries concerning rights for the commercial use of 
this invention should be addressed to: 
NASA Patent Counsel 
Mail Stop 500.113 
Lewis Research Center 
21000 Brookpark Road 
Cleveland, Ohio 44135
Source: James E. Vrancik 
Lewis Research Center 
(LEW-1 1797)
. 
. 
. 
B73-10308	 Category 02


Inexpensive programmable computer clock

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server