Low-voltage continuous-time linear equalizer for digital video applications

This thesis presents a low-voltage continuous-time linear equalizer for the digital video application of 1080p HD video with a data rate of 3 Gbps. The equalizer was designed in the CMOS 45 nm technology with a supply voltage of 1V and bias current of 1.5 mA. The equalizer has a variable gain, which can be adjusted to suit the cable length and physical parameters. The circuit design of the equalizer filter includes a 3-stage filter, where each stage has been implemented as a variable gain amplifier along with a linear transconductance amplifier as a gain control stage. The equalizer is capable of compensating for the loss of a coaxial cable within the range 0-240 m in length, with each stage compensating for a cable of 80 m. The circuit design of the equalizer was implemented in the CMOS 45 nm technology in Cadence Virtuoso. The equalizer was also tested in Matlab, using the model of the coaxial cable to demonstrate the equalization of the data. The transient results of the equalized data, as well as the eye diagrams, are presented in this work

Design of an adaptive cable equalizer using 0.5 [mu]m [i.e. micrometer] CMOS process

Data transmitted over a long length of cable at high rates must be equalized in order to compensate for the loss and phase dispersion of the cable. The more the cable length, the more the loss is in it. As the data transfer rate is increasing, more bandwidth is needed and the data communication industries are demanding an equalizer system with more bandwidth. A pole-zero model for the coax cable- equalizer is developed which shows that the poles and zeros of the cable transfer function decrease linearly with the increase of the cable length. Thus an adaptive equalizer system has been designed where the length of the cable will be estimated through the peak detector circuitry and the equalizer filter will be tuned automatically according to the estimated cable length using this linearity. All the circuits of the system have been designed using AMI 0.5µm CMOS technology and simulated on Cadence\u27s Spectre tools

차세대 자동차용 카메라 데이터 통신을 위한 비대칭 동시 양방향 송수신기의 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.본 학위 논문에서는 차세대 자동차용 카메라 링크를 위해 높은 속도의 4레벨 펄스 진폭 변조 신호와 낮은 속도의 2레벨 펄스 진폭 변조 신호를 통신하는 비대칭 동시 양방향 송수신기의 설계 기술에 대해 제안하고 검증되었다. 첫번째 프로토타입 설계에서는, 10B6Q 직류 밸런스 코드를 탑재한 4레벨 펄스 진폭 변조 송신기와 고정된 데이터와 참조 레벨을 가지는 4레벨 펄스 진폭 변조 적응형 수신기에 대한 내용이 기술되었다. 4레벨 펄스 진폭 변조 송신기에서는 교류 연결 링크 시스템에 대응하기 위한 면적 및 전력 효율성이 좋은 10B6Q 코드가 제안되었다. 이 코드는 직류 밸런스를 맞추고 연속적으로 같은 심볼을 가지는 길이를 6개로 제한 시킨다. 비록 여기서는 입력 데이터 길이 10비트를 사용하였지만, 제안된 기술은 카메라의 다양한 데이터 타입에 대응할 수 있도록 입력 데이터 길이에 대한 확장성을 가진다. 반면, 4레벨 펄스 진폭 변조 적응형 수신기에서는, 샘플러의 옵셋을 최적으로 제거하여 더 낮은 비트에러율을 얻기 위해서, 기존의 데이터 및 참조 레벨을 조절하는 대신, 이 레벨들은 고정시키고 가변 게인 증폭기를 적응형으로 조절하도록 하였다. 상기 10B6Q 코드 및 고정 데이터 및 참조레벨 기술을 가진 프로토타입 칩들은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었고 칩 온 보드 형태로 평가되었다. 10B6Q 코드는 합성 게이트 숫자는 645개와 함께 단 0.0009 mm2 의 면적 만을 차지한다. 또한, 667 MHz 동작 주파수에서 단 0.23 mW 의 전력을 소모한다. 10B6Q 코드를 탑재한 송신기에서 8-Gb/s 4레벨 펄스 진폭 변조 신호를 고정 데이터 및 참조 레벨을 가지는 적응형 수신기로 12-m 케이블 (22-dB 채널 로스) 을 통해서 보낸 결과 최소 비트 에러율 108 을 달성하였고, 비트 에러율 105 에서는 아이 마진이 0.15 UI x 50 mV 보다 크게 측정되었다. 송수신기를 합친 전력 소모는 65.2 mW (PLL 제외) 이고, 성과의 대표수치는 0.37 pJ/b/dB 를 보여주었다. 첫번째 프로토타입 설계을 포함하여 개선된 두번째 프로토타입 설계에서는, 12-Gb/s 4레벨 펄스 진폭 변조 정방향 채널 신호와 125-Mb/s 2레벨 펄스 진폭 변조 역방향 채널 신호를 탑재한 비대칭 동시 양방향 송수신기에 대해 기술되고 검증되었다. 제안된 넓은 선형 범위를 가지는 하이브리드는 gmC 저대역 통과 필터와 에코 제거기와 함께 아웃바운드 신호를 24 dB 이상 효율적으로 감소시켰다. 또한, 넓은 선형 범위를 가지는 하이브리드와 함께 게인 감소기를 형성하게 되는 선형 범위 증폭기를 통해 4레벨 펄스 진폭 변조 신호의 선형성과 진폭의 트레이드 오프 관계를 깨는 것이 가능하였다. 동시 양방향 송수신기 칩은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었다. 상기 설계 기술들을 이용하여, 4레벨 펄스 진폭 변조 및 2레벨 펄스 진폭 변조 송수신기 모두 5m 채널 (채널 로스 15.9 dB) 에서 1E-12 보다 낮은 비트 에러율을 달성하였고, 총 78.4 mW 의 전력 소모를 기록하였다. 종합적인 송수신기는 성과 대표지표로 0.41 pJ/b/dB 와 함께 동시 양방향 통신 아래에서 4레벨 펄스 진폭 변조 신호 및 2레벨 펄스 진폭 변조 신호 각각에서 아이 마진 0.15 UI 와 0.57 UI 를 달성하였다. 이 수치는 성과 대표지표 0.5 이하를 가지는 기존 동시 양방향 송수신기와의 비교에서 최고의 아이 마진을 기록하였다.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 초 록 106박

High-speed equalization and transmission in electrical interconnections

The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm × 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10−11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAX® backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10−8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

Broadband Receiver Electronic Circuits for Fiber-Optical Communication Systems

The exponential growth of internet traffic drives datacenters to constantly improve their capacity. As the copper based network infrastructure is being replaced by fiber-optical interconnects, new industrial standards for higher datarates are required. Several research and industrial organizations are aiming towards 400 Gb Ethernet and beyond, which brings new challenges to the field of high-speed broadband electronic circuit design. Replacing OOK with higher M-ary modulation formats and using higher datarates increases network capacity but at the cost of power. With datacenters rapidly becoming significant energy consumers on the global scale, the energy efficiency of the optical interconnect transceivers takes a primary role in the development of novel systems. There are several additional challenges unique in the design of a broadband shortreach fiber-optical receiver system. The sensitivity of the receiver depends on the noise performance of the PD and the electronics. The overall system noise must be optimized for the specific application, modulation scheme, PD and VCSEL characteristics. The topology of the transimpedance amplifier affects the noise and frequency response of the PD, so the system must be optimized as a whole. Most state-of-the-art receivers are built on high-end semiconductor SiGe and InP technologies. However, there are still several design decisions to be made in order to get low noise, high energy efficiency and adequate bandwidth. In order to overcome the frequency limitations of the optoelectronic components, bandwidth enhancement and channel equalization techniques are used. In this work several different blocks of a receiver system are designed and characterized. A broadband, 50 GHz bandwidth CB-based TIA and a tunable gain equalizer are designed in a 130 nm SiGe BiCMOS process. An ultra-broadband traveling wave amplifier is presented, based on a 250 nm InP DHBT technology demonstrating a 207 GHz bandwidth. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback, based on a 130 nm InP DHBT technology are designed and compared

Wideband integrated circuits for optical communication systems

The exponential growth of internet traffic drives datacenters to constantly improvetheir capacity. Several research and industrial organizations are aiming towardsTbps Ethernet and beyond, which brings new challenges to the field of high-speedbroadband electronic circuit design. With datacenters rapidly becoming significantenergy consumers on the global scale, the energy efficiency of the optical interconnecttransceivers takes a primary role in the development of novel systems. Furthermore,wideband optical links are finding application inside very high throughput satellite(V/HTS) payloads used in the ever-expanding cloud of telecommunication satellites,enabled by the maturity of the existing fiber based optical links and the hightechnology readiness level of radiation hardened integrated circuit processes. Thereare several additional challenges unique in the design of a wideband optical system.The overall system noise must be optimized for the specific application, modulationscheme, PD and laser characteristics. Most state-of-the-art wideband circuits are builton high-end semiconductor SiGe and InP technologies. However, each technologydemands specific design decisions to be made in order to get low noise, high energyefficiency and adequate bandwidth. In order to overcome the frequency limitationsof the optoelectronic components, bandwidth enhancement and channel equalizationtechniques are used. In this work various blocks of optical communication systems aredesigned attempting to tackle some of the aforementioned challenges. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback,are designed and measured, utilizing a state-of-the-art 130 nm InP DHBT technology.A modular equalizer block built in 130 nm SiGe HBT technology is presented. Threeultra-wideband traveling wave amplifiers, a 4-cell, a single cell and a matrix single-stage, are designed in a 250 nm InP DHBT process to test the limits of distributedamplification. A differential VCSEL driver circuit is designed and integrated in a4x 28 Gbps transceiver system for intra-satellite optical communications based in arad-hard 130nm SiGe process

Modelling and performance analysis of multigigabit serial interconnects using real number based analog verification methods

The increasing importance of multigigabit transceiver circuits in modern chip design calls for new methods of analyzing and integrating these challenging building blocks. This work presents a design and analysis framework basend on the SystemVerilog real number modeling ansatz. It further extends the simulation possibilities thus obtained by introducing additional higher level numeric modelling and evaluation methods to support multigigabit statistical link budgeting procedures based on the Peak Distortion Algorithm

Equalization Architectures for High Speed ADC-Based Serial I/O Receivers

The growth in worldwide network traffic due to the rise of cloud computing and wireless video consumption has required servers and routers to support increased serial I/O data rates over legacy channels with significant frequency-dependent attenuation. For these high-loss channel applications, ADC-based high-speed links are being considered due to their ability to enable powerful digital signal processing (DSP) algorithms for equalization and symbol detection. Relative to mixed-signal equalizers, digital implementations offer robustness to process, voltage and temperature (PVT) variations, are easier to reconfigure, and can leverage CMOS technology scaling in a straight-forward manner. Despite these advantages, ADC-based receivers are generally more complex and have higher power consumption relative to mixed-signal receivers. The ensuing digital equalization can also consume a significant amount of power which is comparable to the ADC contribution. Novel techniques to reduce complexity and improve power efficiency, both for the ADC and the subsequent digital equalization, are necessary. This dissertation presents efficient modeling and implementation approaches for ADC-based serial I/O receivers. A statistical modeling framework is developed, which is able to capture ADC related errors, including quantization noise, INL/DNL errors and time interleaving mismatch errors. A novel 10GS/s hybrid ADC-based receiver, which combines both embedded and digital equalization, is then presented. Leveraging a time-interleaved asynchronous successive approximation ADC architecture, a new structure for 3-tap embedded FFE inside the ADC with low power/area overhead is used. In addition, a dynamically-enabled digital 4-tap FFE + 3-tap DFE equalizer architecture is introduced, which uses reliable symbol detection to achieve remarkable savings in the digital equalization power. Measurement results over several FR4 channels verify the accuracy of the modeling approach and the effectiveness of the proposed receiver. The comparison of the fabricated prototype against state-of-the-art ADC-based receivers shows the ability of the proposed archi-tecture to compensate for the highest loss channel, while achieving the best power efficiency among other works