Analog hardware security and hardware authentication

Hardware security and hardware authentication have become more and more important concerns in the manufacture of trusted integrated circuits. In this dissertation, a detailed study of hardware Trojans in analog circuits characterized by the presence of extra operating points or modes is presented. In a related study, a counterfeit countermeasure method based upon PUF authentication circuits is proposed for addressing the growing proliferation of counterfeit integrated circuits in the supply chain. Most concerns about hardware Trojans in semiconductor devices are based upon an implicit assumption that attackers will focus on embedding Trojans in digital hardware by making malicious modifications to the Boolean operation of a circuit. In stark contrast, hardware Trojans can be easily embedded in some of the most basic analog circuits. In this work, a particularly insidious class of analog hardware Trojans that require no architectural modifications, no area or power overhead, and prior to triggering, that leave no signatures in any power domains or delay paths is introduced. The Power/Architecture/Area/Signature Transparent (PAAST) characteristics help the Trojan “hide” and make them very difficult to detect with existing hardware Trojan detection methods. Cleverly hidden PAAST Trojans are nearly impossible to detect with the best simulation and verification tools, even if a full and accurate disclosure of the circuit schematic and layout is available. Aside from the work of the author of this dissertation and her classmates, the literature is void of discussions of PAAST analog hardware Trojans. In this work, examples of circuits showing the existence of PAAST analog hardware Trojans are given, the PAAST characteristics of these types of hardware Trojans are discussed, and heuristic detection methods that can help to detect these analog hardware Trojans are proposed. Another major and growing problem in the modern IC supply chain is the proliferation of counterfeit chips that are often characterized by different or inferior performance characteristics and reduced reliability when compared with authentic parts. A counterfeit countermeasure method is proposed that should lower the entry barrier for major suppliers of commercial off the shelf (COTS) parts to offer authenticated components to the military and other customers that have high component reliability requirements. The countermeasure is based upon a PUF authentication circuit that requires no area, pin, or power overhead, and causes no degradation of performance of existing and future COTS components

Complementarity methods in the analysis of piecewise linear dynamical systems

The main object of this thesis is a class of piecewise linear dynamical systems that are related both to system theory and to mathematical programming. The dynamical systems in this class are known as complementarity systems. With regard to these nonlinear and nonsmooth dynamical systems, the research in the thesis concentrates on two themes: well-posedness and approximations. The well-posedness issue, in the sense of existence and uniqueness of solutions, is of considerable importance from a model validation point of view. In the thesis, sufficient conditions are established for the well-posedness of complementarity systems. Furthermore, an investigation is made of the convergence of approximations of these systems with an eye towards simulation

Design and verification approaches for reliability and functional safety of analog integrated circuits

New breakthroughs in semiconductor design have enabled a rapid integration of semiconductor chips into systems that affect all aspects of the society. Examples of emerging systems include spacecraft, Internet of Things (IoT), intelligent automotive, and bio-implantable devices. Many of these systems are mission-critical or safety-critical, meaning that failure or malfunction may lead to severe economical losses, environmental damages or risks to human lives. In addition to performances improvement, the reliability and functional safety of the underlying integrated circuit (IC) have attracted more and more attention and have posed grand challenges for semiconductor industries. This dissertation introduces an approach for high performance voltage reference design and investigates two subjects that improve the reliability and functional safety of analog circuits. The first part of this dissertation studies design strategies of a low temperature-coefficient voltage reference generator, which is a fundamental building block and determines the maximum achievable performance of almost all analog/mixed-signal systems. The proposed method is targeted at extracting a physical quantity of the silicon bandgap, and has the potential of designing a voltage reference that has qualitatively better temperature dependence. An implementation of the proposed approach in GlobalFoundries 130nm process shows that the design can achieve temperature coefficients as low as 0.7ppm/°C over a temperature range of -40°C to 125°C over all process corners. The second part of this dissertation focuses on multi-states verification of analog circuits. The multiple DC equilibrium points or multi-states problem traces back to IC design. It is a well-known problem in many basic self-stabilized analog circuits because of the existence of positive feedback loops (PFLs). This work proposes systematic and automatic approaches for locating all PFLs to identify circuits vulnerable to undesired equilibrium states and methods for automatically identifying break-points to break all PFLs in the vulnerable circuits. The proposed methods make it possible to efficiently identify a circuit’s vulnerability to undesired operating points by considering circuit topology only, without the need for finding all possible solutions to a set of simultaneous nonlinear equations which is an open problem with no solution. Moreover, the automatic break-points identification enables easy use of homotopy analysis to guarantee absence of undesired states. The third part of this dissertation focuses on fault coverage simulation of analog circuits. This work describe two methods, one is to reduce the fault coverage estimation time and the other is to improve the fault coverage for analog circuits. The first method incorporates graph theory and sensitivity analysis and leads to dramatic reduction in fault coverage simulation time by 10’s of times for a moderately sized analog circuit. The second method discusses a systematic test-points selection technique to improve the analog fault coverage with simple DC tests and a concurrent sampling technique for monitoring these points. This work could be applied to manufacturing testing or for real-time fault detection

Electric field imaging

Thesis (Ph.D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts & Sciences, 1999.Includes bibliographical references (p. 213-216).The physical user interface is an increasingly significant factor limiting the effectiveness of our interactions with and through technology. This thesis introduces Electric Field Imaging, a new physical channel and inference framework for machine perception of human action. Though electric field sensing is an important sensory modality for several species of fish, it has not been seriously explored as a channel for machine perception. Technological applications of field sensing, from the Theremin to the capacitive elevator button, have been limited to simple proximity detection tasks. This thesis presents a solution to the inverse problem of inferring geometrical information about the configuration and motion of the human body from electric field measurements. It also presents simple, inexpensive hardware and signal processing techniques for making the field measurements, and several new applications of electric field sensing. The signal processing contribution includes synchronous undersampling, a narrowband, phase sensitive detection technique that is well matched to the capabilities of contemporary microcontrollers. In hardware, the primary contributions are the School of Fish, a scalable network of microcontroller-based transceive electrodes, and the LazyFish, a small footprint integrated sensing board. Connecting n School of Fish electrodes results in an array capable of making heterodyne measurements of any or all n(n - 1) off-diagonal entries in the capacitance matrix. The LazyFish uses synchronous undersampling to provide up to 8 high signal-to-noise homodyne measurements in a very small package. The inverse electrostatics portion of the thesis presents a fast, general method for extracting geometrical information about the configuration and motion of the human body from field measurements. The method is based on the Sphere Expansion, a novel fast method for generating approximate solutions to the Laplace equation. Finally, the thesis describes a variety of applications of electric field sensing, many enabled by the small footprint of the LazyFish. To demonstrate the School of Fish hardware and the Sphere Expansion inversion method, the thesis presents 3 dimensional position and orientation tracking of two hands.by Joshua Reynolds Smith.Ph.D

Advanced Information Systems and Technologies

This book comprises the proceedings of the V International Scientific Conference "Advanced Information Systems and Technologies, AIST-2017". The proceeding papers cover issues related to system analysis and modeling, project management, information system engineering, intelligent data processing computer networking and telecomunications. They will be useful for students, graduate students, researchers who interested in computer science

Advanced Information Systems and Technologies

This book comprises the proceedings of the V International Scientific Conference "Advanced Information Systems and Technologies, AIST-2017". The proceeding papers cover issues related to system analysis and modeling, project management, information system engineering, intelligent data processing computer networking and telecomunications. They will be useful for students, graduate students, researchers who interested in computer science

Hilbert-Huang Transform: biosignal analysis and practical implementation

Any system, however trivial, is subjected to data analysis on the signals it produces. Over the last 50 years the influx of new techniques and expansions of older ones have allowed a number of new applications, in a variety of fields, to be analysed and to some degree understood. One of the industries that is benefiting from this growth is the medical field and has been further progressed with the growth of interdisciplinary collaboration. From a signal processing perspective, the challenge comes from the complex and sometimes chaotic nature of the signals that we measure from the body, such as those from the brain and to some degree the heart. In this work we will make a contribution to dealing with such systems, in the form of a recent time-frequency data analysis method, the Hilbert-Huang Transform (HHT), and extensions to it. This thesis presents an analysis of the state of the art in seizure and heart arrhythmia detection and prediction methods. We then present a novel real-time implementation of the algorithm both in software and hardware and the motivations for doing so. First, we present our software implementation, encompassing realtime capabilities and identifying elements that need to be considered for practical use. We then translated this software into hardware to aid real-time implementation and integration. With these implementations in place we apply the HHT method to the topic of epilepsy (seizures) and additionally make contributions to heart arrhythmias and neonate brain dynamics. We use the HHT and some additional algorithms to quantify features associated with each application for detection and prediction. We also quantify significance of activity in such a way as to merge prediction and detection into one framework. Finally, we assess the real-time capabilities of our methods for practical use as a biosignal analysis tool