Self-Time Circuit Size Optimization For An Input Data Distribution

The analysis is based on the Logical Effort (LE). The LE model used in this work was extracted from SPICE simulation for the TMSC 0.18um process. The performance and energy dissipation of circuits implemented with this approach is 13% and 16% respectively better than circuits designed with previously proposed approaches

Research in the effective implementation of guidance computers with large scale arrays Interim report

Functional logic character implementation in breadboard design of NASA modular compute

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Models of computation: A numeric analysis and performance evaluation

This research seeks to better understand what drives performance in computation. To develop this understanding the researcher investigates the literature on computational performance within the classical and quantum paradigm for both binary and multi-value logic. Based on the findings of the literature the researcher evaluates through an experiment of addition what drives performance and how performance can be improved. For the evaluation of this research, a realist research paradigm employs two research methods. The first is an automaton model of computation to model each of the computing paradigms and computational logic. The second is computational complexity theory for measuring the performance of addition. Through this evaluation the researcher seeks to gain a better understanding of what drives computational performance and how addition can be performed more efficiently. The results of the research lead the researcher to conclude that modernisation of machinery caused the birth start of automated computing and the binary number system in computers. As this research indicated that computation through increasing the radix can improve performance of computation for addition. Based on reported findings in the science of quantum mechanics research, it would be possible to implement a model of computation with increased radix. Through embracing state discrimination/ distinguishability this research calls to review the current quantum computing paradigm based on state duality