Fpga-based Design Of A Maximum-power-point Tracking System For Space A

Satellites need a source of power throughout their missions to help them remain operational for several years. The power supplies of these satellites, provided primarily by solar arrays, must have high efficiencies and low weights in order to meet stringent design constraints. Power conversion from these arrays is required to provide robust and reliable conversion which performs optimally in varying conditions of peak power, solar flux, and occlusion conditions. Since the role of these arrays is to deliver power, one of the principle factors in achieving maximum power output from an array is tracking and holding its maximum-power point. This point, which varies with temperature, insolation, and loading conditions, must be continuously monitored in order to react to rapid changes. Until recently, the control of maximum power point tracking (MPPT) has been implemented in microcontrollers and digital signal processors (DSPs). While DSPs can provide a reasonable performance, they do not provide the advantages that field-programmable gate arrays (FPGA) chips can potentially offer to the implementation of MPPT control. In comparison to DSP implementations, FPGAs offer lower cost implementations since the functions of various components can be integrated onto the same FPGA chip as opposed to DSPs which can perform only DSP-related computations. In addition, FPGAs can provide equivalent or higher performance with the customization potential of an ASIC. Because FPGAs can be reprogrammed at any time, repairs can be performed in-situ while the system is running thus providing a high degree of robustness. Beside robustness, this reprogrammability can provide a high level of (i) flexibility that can make upgrading an MPPT control system easy by merely updating or modifying the MPPT algorithm running on the FPGA chip, and (ii) expandability that makes expanding an FPGA-based MPPT control system to handle multi-channel control. In addition, this reprogrammability provides a level of testability that DSPs cannot match by allowing the emulation of the entire MPPT control system onto the FPGA chip. This thesis proposes an FPGA-based implementation of an MPPT control system suitable for space applications. At the core of this system, the Perturb-and-observe algorithm is used to track the maximum power point. The algorithm runs on an Alera FLEX 10K FPGA chip. Additional functional blocks, such as the ADC interface, FIR filter, dither generator, and DAC interface, needed to support the MPPT control system are integrated within the same FPGA device thus streamlining the part composition of the physical prototype used to build this control system

QuickStep, a system for performance monitoring and debugging parallel applications on the Alewife multiprocessor

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (leaves 77-78).by Sramana Mitra.M.S

Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable

A CUSTOM ARCHITECTURE FOR DIGITAL LOGIC SIMULATION

As VLSI technology advances, designers can pack larger circuits into a single chip. According to the International Technology Roadmap for Semiconductors, in the year 2005, VLSI circuit technology will produce chips with 200 million transistors in total, 40 million logic gates, 2 to 3.5 GHz clock rates, and 160 watts of power-consumption. Recently, Intel announced that they will produce a billion-transistor processor before 2010. However, current design methodologies can only handle tens of millions of transistors in a single design. In this thesis, we focus on the problem of simulating large digital devices at the gate level. While many software solutions to gate-level simulation exist, their performance is limited by the underlying general-purpose workstation architecture. This research defines an architecture that is specifically designed for gate-level logic simulation that is at least an order of magnitude faster than software running on a workstation. We present a custom processor and memory architecture design that can simulate a gate level design orders of magnitude faster than the software simulation, while maintaining 4-levels of signal strength. New primitives are presented and shown to significantly reduce the complexity of simulation. Unlike most simulators, which only use zero or unit time delay models, this research provides a mechanism to handle more complex full-timing delay model at pico-second accuracy. Experimental results and a working prototype will also be presented

Hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnections.

by Lo Wing-yee.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves vii-ix).ABSTRACT --- p.iLIST OF TABLES --- p.ivLIST OF FIGURES --- p.vChapter 1. --- INTRODUCTION --- p.1Chapter 1.1 --- Traditional Design Prototyping --- p.1Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6Chapter 2. --- HARDWARE DESIGNS --- p.9Chapter 2.1 --- Bus Interconnection --- p.9Chapter 2.1.1 --- Fixed buses --- p.9Chapter 2.1.2 --- Programmable buses --- p.12Chapter 2.2 --- Architectural Features --- p.15Chapter 2.2.1 --- Field programmable gate array --- p.15Chapter 2.2.2 --- Microprocessor --- p.15Chapter 2.2.3 --- Memory --- p.16Chapter 2.2.4 --- Buffers --- p.18Chapter 3. --- SOFTWARE TOOLS --- p.20Chapter 3.1 --- Critical Path Analysis --- p.20Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21Chapter 3.1.2 --- Computation time --- p.21Chapter 3.2 --- Circuit Partitioning --- p.23Chapter 3.2.1 --- Partitioning algorithm --- p.24Chapter 3.2.2 --- Effects of partitioning --- p.36Chapter 3.2.3 --- Partitioning parameters --- p.38Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39Chapter 3.3 --- IO Assignments --- p.40Chapter 3.3.1 --- Connect 4 FPGAs --- p.40Chapter 3.3.2 --- Connect 3 FPGAs --- p.42Chapter 3.3.3 --- Connect 2 FPGAs --- p.44Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47Chapter 3.4 --- Other Tools --- p.48Chapter 4. --- STRUCTURE ANALYSIS --- p.49Chapter 5. --- RESULTS --- p.52Chapter 6. --- FUTURE DIRECTION --- p.73Chapter 6.1 --- Other Possible Configurations --- p.73Chapter 6.2 --- Programmable Interconnection --- p.73Chapter 6.3 --- Expandability of UPB --- p.74Chapter 7. --- CONCLUSION --- p.75BIBLIOGRAPHY --- p.viiAPPENDICES --- p.

Méthodologie de génération de plateforme de prototypage à base de multi-fpga

Multi-FPGA based prototyping is no longer optional for hardware/software integration. We can classify multi-FPGA prototyping platforms in three categories: off-the-shelf, custom and cabling. The cabling platform is semi off-the-shelf and semi custom. Nevertheless, crafting a custom and a cabling platform is today a manual process, which is time-consuming. The performance and the cost of the platform lie on the FPGA expertise and SoC DUT knowledge of the engineers. Compared to OTS platforms, the added value, in terms of performance, of cabling or custom platforms can be heavily impaired by an inefficient board design. Moreover, FPGA I/Os are becoming a scarce resource, worsening the inter-FPGA bandwidth generation after generation. Therefore, it becomes more and more difficult to prototype an SoC/ASIC design at proper performance. The contributions of the manuscript are: (1). An automatic implementation flow for an OTS platform is proposed. (2). An automatic design flow for creating a custom platform is proposed, thus increasing the productivity, enabling the board exploration, and optimizing cost and performance. (3). The cabling platform is proposed where one board is composed of one FPGA and several connectors, with an algorithm to automatically find a solution for the cable distribution. (4). Thanks to the developed automatic tools, the three different multi-FPGA platforms are compared. The custom platform always achieves better performance and lower deployment cost, but still with 3-5 months in time of availability. If the performance or the deployment cost are not rigorous constraints, the cabling platform offers an attractive alternative compared to others.Face à la difficulté de l’intégration matériel/logiciel, le prototypage à base de multi-FPGA devient obligatoire dans la vérification pré-silicium. Les plateformes de prototypage peuvent être classées en trois catégories: OTS, sur mesure et câblées. La plateforme câblée est semi OTS et semi sur mesure. Néanmoins, la création d’une plateforme sur mesure et câblée est un processus manuel et chronophage. La performance et le coût de la plateforme dépend de l'expérience de concepteurs en expertise de FPGA et connaissance du système sur puce. Par rapport à des plateformes OTS, la valeur ajoutée, en terme de performance, des plateformes câblées ou sur mesure peuvent être fortement dégradée par une carte inefficace. En plus, FPGA E/S devient une ressource rare, aggravant la bande passante inter-FPGA. Par conséquent, il devient de plus en plus difficile de prototyper un design à une performance satisfaisante. Les contributions sont: (1). Un flot de implémentation automatique pour une plateforme OTS. (2). Un flot de conception automatique pour créer une plateforme sur mesure, ainsi augmentant la productivité, permettant l’exploration de carte et optimisant le coût et la performance. (3). La plateforme câblée avec un algorithme permettant automatiquement de trouver une solution pour la distribution des câbles. (4). Grâce aux flots automatique, les trois plateformes sont comparées. La plateforme sur mesure toujours réalise plus de performance et moins de coût de déploiement, mais encore avec 3-5 mois en temps de disponibilité. Si la performance ou le coût de déploiement ne sont pas les contraintes strictes, la plateforme câblée est une alternative intéressante par rapport aux autres