Some aspects of traffic control and performance evaluation of ATM networks

The emerging high-speed Asynchronous Transfer Mode (ATM) networks are expected to integrate through statistical multiplexing large numbers of traffic sources having a broad range of statistical characteristics and different Quality of Service (QOS) requirements. To achieve high utilisation of network resources while maintaining the QOS, efficient traffic management strategies have to be developed. This thesis considers the problem of traffic control for ATM networks. The thesis studies the application of neural networks to various ATM traffic control issues such as feedback congestion control, traffic characterization, bandwidth estimation, and Call Admission Control (CAC). A novel adaptive congestion control approach based on a neural network that uses reinforcement learning is developed. It is shown that the neural controller is very effective in providing general QOS control. A Finite Impulse Response (FIR) neural network is proposed to adaptively predict the traffic arrival process by learning the relationship between the past and future traffic variations. On the basis of this prediction, a feedback flow control scheme at input access nodes of the network is presented. Simulation results demonstrate significant performance improvement over conventional control mechanisms. In addition, an accurate yet computationally efficient approach to effective bandwidth estimation for multiplexed connections is investigated. In this method, a feed forward neural network is employed to model the nonlinear relationship between the effective bandwidth and the traffic situations and a QOS measure. Applications of this approach to admission control, bandwidth allocation and dynamic routing are also discussed. A detailed investigation has indicated that CAC schemes based on effective bandwidth approximation can be very conservative and prevent optimal use of network resources. A modified effective bandwidth CAC approach is therefore proposed to overcome the drawback of conventional methods. Considering statistical multiplexing between traffic sources, we directly calculate the effective bandwidth of the aggregate traffic which is modelled by a two-state Markov modulated Poisson process via matching four important statistics. We use the theory of large deviations to provide a unified description of effective bandwidths for various traffic sources and the associated ATM multiplexer queueing performance approximations, illustrating their strengths and limitations. In addition, a more accurate estimation method for ATM QOS parameters based on the Bahadur-Rao theorem is proposed, which is a refinement of the original effective bandwidth approximation and can lead to higher link utilisation

Dynamic bandwidth allocation in ATM networks

Includes bibliographical references.This thesis investigates bandwidth allocation methodologies to transport new emerging bursty traffic types in ATM networks. However, existing ATM traffic management solutions are not readily able to handle the inevitable problem of congestion as result of the bursty traffic from the new emerging services. This research basically addresses bandwidth allocation issues for bursty traffic by proposing and exploring the concept of dynamic bandwidth allocation and comparing it to the traditional static bandwidth allocation schemes

Application of learning algorithms to traffic management in integrated services networks.

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN027131 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Design of traffic shaper / scheduler for packet switches and DiffServ networks : algorithms and architectures

The convergence of communications, information, commerce and computing are creating a significant demand and opportunity for multimedia and multi-class communication services. In such environments, controlling the network behavior and guaranteeing the user\u27s quality of service is required. A flexible hierarchical sorting architecture which can function either as a traffic shaper or a scheduler according to the requirement of the traffic load is presented to meet the requirement. The core structure can be implemented as a hierarchical traffic shaper which can support a large number of connections with a wide variety of rates and burstiness without the loss of the granularity in cells\u27 conforming departure time. The hierarchical traffic shaper can implement the exact sorting scheme with a substantial reduced memory size by using two stages of timing queues, and with substantial reduction in complexity, without introducing any sorting inaccuracy. By setting a suitable threshold to the length of the departure queue and using a lookahead algorithm, the core structure can be converted to a hierarchical rateadaptive scheduler. Based on the traffic load, it can work as an exact sorting traffic shaper or a Generic Cell Rate Algorithm (GCRA) scheduler. Such a rate-adaptive scheduler can reduce the Cell Transfer Delay and the Maximum Memory Occupancy greatly while keeping the fairness in the bandwidth assignment which is the inherent characteristic of GCRA. By introducing a best-effort queue to accommodate besteffort traffic, the hierarchical sorting architecture can be changed to a near workconserving scheduler. It assigns remaining bandwidth to the best-effort traffic so that it improves the utilization, of the outlink while it guarantees the quality of service requirements of those services which require quality of service guarantees. The inherent flexibility of the hierarchical sorting architecture combined with intelligent algorithms determines its multiple functions. Its implementation not only can manage buffer and bandwidth resources effectively, but also does not require no more than off-the-shelf hardware technology. The correlation of the extra shaping delay and the rate of the connections is revealed, and an improved fair traffic shaping algorithm, Departure Event Driven plus Completing Service Time Resorting algorithm, is presented. The proposed algorithm introduces a resorting process into Departure Event Driven Traffic Shaping Algorithm to resolve the contention of multiple cells which are all eligible for transmission in the traffic shaper. By using the resorting process based on each connection\u27s rate, better fairness and flexibility in the bandwidth assignment for connections with wide range of rates can be given. A Dual Level Leaky Bucket Traffic Shaper(DLLBTS) architecture is proposed to be implemented at the edge nodes of Differentiated Services Networks in order to facilitate the quality of service management process. The proposed architecture can guarantee not only the class-based Service Level Agreement, but also the fair resource sharing among flows belonging to the same class. A simplified DLLBTS architecture is also given, which can achieve the goals of DLLBTS while maintain a very low implementation complexity so that it can be implemented with the current VLSI technology. In summary, the shaping and scheduling algorithms in the high speed packet switches and DiffServ networks are studied, and the intelligent implementation schemes are proposed for them

Adaptive reservation TDMA protocol for wireless multimedia traffic

An Adaptive Reservation Time Division Multiple Access (AR-TDMA) control protocol for Wireless Asynchronous Transfer Mode (WATM) networks is proposed in this paper. AR-TDMA combines the advantages of distributed access and centralised control for transporting Constant Bit Rate (CBR), Variable Bit Rate (VBR) and Available Bit Rate (ABR) traffic efficiently over a wireless channel. The contention slots access for reservation requests is governed by two protocols, the Adaptive Framed Pseudo-Bayesian Aloha with Adaptive Slot Assignment (AFPBAASA) protocol and the Framed Pseudo-Bayesian Aloha with Adaptively Prioritised Controlled Capture (FPBAAPCC) protocol. Both protocols provide different access priorities to the control packets in order to improve the Quality-of-Service (QoS) offered to time sensitive connections. AR-TDMA also features a novel integrated resource allocation algorithm that efficiently schedules terminals’ reserved access to the wireless ATM channel by considering their requested bandwidth and QoS. Integration of CBR, voice, VBR, data and control traffic over the wireless ATM channel using the proposed AR-TDMA protocol is considered in the paper. The performance of the AR-TDMA in conjunction with the AFPBA-ASA protocol and FPBA-APCC protocol has been investigated and the simulation results are presented showing that the protocol satisfies the required QoS of each traffic category while providing a highly efficient utilisation of approximately 96% for the wireless ATM channel

From burstiness characterisation to traffic control strategy : a unified approach to integrated broadbank networks

The major challenge in the design of an integrated network is the integration and support of a wide variety of applications. To provide the requested performance guarantees, a traffic control strategy has to allocate network resources according to the characteristics of input traffic. Specifically, the definition of traffic characterisation is significant in network conception. In this thesis, a traffic stream is characterised based on a virtual queue principle. This approach provides the necessary link between network resources allocation and traffic control. It is difficult to guarantee performance without prior knowledge of the worst behaviour in statistical multiplexing. Accordingly, we investigate the worst case scenarios in a statistical multiplexer. We evaluate the upper bounds on the probabilities of buffer overflow in a multiplexer, and data loss of an input stream. It is found that in networks without traffic control, simply controlling the utilisation of a multiplexer does not improve the ability to guarantee performance. Instead, the availability of buffer capacity and the degree of correlation among the input traffic dominate the effect on the performance of loss. The leaky bucket mechanism has been proposed to prevent ATM networks from performance degradation due to congestion. We study the leaky bucket mechanism as a regulation element that protects an input stream. We evaluate the optimal parameter settings and analyse the worst case performance. To investigate its effectiveness, we analyse the delay performance of a leaky bucket regulated multiplexer. Numerical results show that the leaky bucket mechanism can provide well-behaved traffic with guaranteed delay bound in the presence of misbehaving traffic. Using the leaky bucket mechanism, a general strategy based on burstiness characterisation, called the LB-Dynamic policy, is developed for packet scheduling. This traffic control strategy is closely related to the allocation of both bandwidth and buffer in each switching node. In addition, the LB-Dynamic policy monitors the allocated network resources and guarantees the network performance of each established connection, irrespective of the traffic intensity and arrival patterns of incoming packets. Simulation studies demonstrate that the LB-Dynamic policy is able to provide the requested service quality for heterogeneous traffic in integrated broadband networks

Performance analysis of error recovery and congestion control in high-speed networks

In the past few years, Broadband Integrated Services Digital Network (B-ISDN) has received increasing attention as a communication architecture capable of supporting multimedia applications. Among the techniques proposed to implement B-ISDN, Asynchronous Transfer Mode (ATM) is considered to be the most promising transfer technique because of its efficiency and flexibility.In ATM networks, the performance bottleneck of the network, which was once the channel transmission speed, is shifted to the processing speed at the network switching nodes and the propagation delay of the channel. This shift is because the high-speed channel increases the ratio of processing time to packet transmission time and also the ratio of propagation delay to packet transmission time. The increased processing overhead makes it difficult to implement hop-by-hop schemes, which may impose prohibitably high processing at each switching node. The increased propagation delay overhead makes traffic control in ATM a challenge since a large number of packets can be in transit between two ATM switching nodes. Because of these fundamental changes, control schemes developed for traditional networks may not perform efficiently, and thus, new network architectures (congestion control schemes, error control schemes, etc.) are required in ATM networks.In this dissertation, we first present an extensive survey of various traffic control schemes and network protocols for ATM networks. In this survey, possible traffic control schemes are examined, and problems of those schemes and their possible solutions are presented. Next, we investigate two key research issues in ATM networks (and other types of high-speed networks): the effects of protocol-processing overhead and the efficiency of traffic control schemes.We first investigate the effects of protocol-processing overhead on the performance of error recovery schemes. Specifically, we investigate the performance trade-offs between link-by-link and edge-to-edge error recovery schemes. Our results show that for a network with high-speed/low-error-rate channels, an edge-to-edge scheme gives a smaller delay than a link-by-link scheme. We then investigate the effectiveness of a priority packet discarding scheme, a congestion control mechanism suitable for high-speed networks. We derive loss probabilities for each stream and investigate the impact of burstiness of traffic streams on the performance of individual streams

A hybrid queueing model for fast broadband networking simulation

PhDThis research focuses on the investigation of a fast simulation method for broadband telecommunication networks, such as ATM networks and IP networks. As a result of this research, a hybrid simulation model is proposed, which combines the analytical modelling and event-driven simulation modelling to speeding up the overall simulation. The division between foreground and background traffic and the way of dealing with these different types of traffic to achieve improvement in simulation time is the major contribution reported in this thesis. Background traffic is present to ensure that proper buffering behaviour is included during the course of the simulation experiments, but only the foreground traffic of interest is simulated, unlike traditional simulation techniques. Foreground and background traffic are dealt with in a different way. To avoid the need for extra events on the event list, and the processing overhead, associated with the background traffic, the novel technique investigated in this research is to remove the background traffic completely, adjusting the service time of the queues for the background traffic to compensate (in most cases, the service time for the foreground traffic will increase). By removing the background traffic from the event-driven simulator the number of cell processing events dealt with is reduced drastically. Validation of this approach shows that, overall, the method works well, but the simulation using this method does have some differences compared with experimental results on a testbed. The reason for this is mainly because of the assumptions behind the analytical model that make the modelling tractable. Hence, the analytical model needs to be adjusted. This is done by having a neural network trained to learn the relationship between the input traffic parameters and the output difference between the proposed model and the testbed. Following this training, simulations can be run using the output of the neural network to adjust the analytical model for those particular traffic conditions. The approach is applied to cell scale and burst scale queueing to simulate an ATM switch, and it is also used to simulate an IP router. In all the applications, the method ensures a fast simulation as well as an accurate result