Genuine lab experiences for students in resource constrained environments: The RealLab with integrated intelligent assessment.

Laboratory activities are indispensable for developing engineering skills. Computer Aided Learning (CAL) tools can be used to enhance laboratory learning in various ways, the latest approach being the virtual laboratory technique that emulates traditional laboratory processes. This new approach makes it possible to give students complete and genuine laboratory experiences in situations constrained by limited resources in the provision of laboratory facilities and infrastructure and/or where there is need for laboratory education, for large classes, with only one laboratory stand. This may especially be the case in countries in transition. Most existing virtual laboratories are not available for purchase. Where they are, they may not be cost friendly for resource constrained environments. Also, most do not integrate any form of assessment structure. In this paper, we present a very cost friendly virtual laboratory solution for genuine laboratory experiences in resource constrained environments, with integrated intelligent assessment

The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs)

Design methods for fault-tolerant navigation computers

Design methods for fault tolerant navigation computer

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

Computer aided electronic circuit design Status report, Dec. 1, 1967 - May 31, 1968

Computer aided electronic circuit desig

Battery choice and management for New Generation Electric Vehicles

Different types of electric vehicles (EVs) have been recently designed with the aim of solving pollution problems caused by the emission of gasoline-powered engines. Environmental problems promote the adoption of new-generation electric vehicles for urban transportation. As it is well known, one of the weakest points of electric vehicles is the battery system. Vehicle autonomy and, therefore, accurate detection of battery state of charge (SoC) together with battery expected life, i.e., battery state of health, are among the major drawbacks that prevent the introduction of electric vehicles in the consumer market. The electric scooter may provide the most feasible opportunity among EVs. They may be a replacement product for the primary-use vehicle, especially in Europe and Asia, provided that drive performance, safety, and cost issues are similar to actual engine scooters. The battery system choice is a crucial item, and thanks to an increasing emphasis on vehicle range and performance, the Li-ion battery could become a viable candidate. This paper deals with the design of a battery pack based on Li-ion technology for a prototype electric scooter with high performance and autonomy. The adopted battery system is composed of a suitable number of cells series connected, featuring a high voltage level. Therefore, cell equalization and monitoring need to be provided. Due to manufacturing asymmetries, charge and discharge cycles lead to cell unbalancing, reducing battery capacity and, depending on cell type, causing safety troubles or strongly limiting the storage capacity of the full pack. No solution is available on the market at a cheap price, because of the required voltage level and performance, therefore, a dedicated battery management system was designed, that also includes a battery SoC monitoring. The proposed solution features a high capability of energy storing in braking conditions, charge equalization, overvoltage and undervoltage protection and, obviously, SoC information in order to optimize autonomy instead of performance or vice-versa

Focal Spot, Spring 1990

https://digitalcommons.wustl.edu/focal_spot_archives/1054/thumbnail.jp

Color Capable Sub-Pixel Resolving Optofluidic Microscope and Its Application to Blood Cell Imaging for Malaria Diagnosis

Miniaturization of imaging systems can significantly benefit clinical diagnosis in challenging environments, where access to physicians and good equipment can be limited. Sub-pixel resolving optofluidic microscope (SROFM) offers high-resolution imaging in the form of an on-chip device, with the combination of microfluidics and inexpensive CMOS image sensors. In this work, we report on the implementation of color SROFM prototypes with a demonstrated optical resolution of 0.66 µm at their highest acuity. We applied the prototypes to perform color imaging of red blood cells (RBCs) infected with Plasmodium falciparum, a particularly harmful type of malaria parasites and one of the major causes of death in the developing world

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente